Simple Memory Decoder GAL

8BIT · Post by **8BIT** » Thu Oct 21, 2010 12:23 pm

PontusO wrote:

Daryl,

Maybe I misunderstood your statement regarding anding terms but this is as far as I know: Each product term in a 20V8 is essentially a 32-input AND gate. Allowing you to create AND equations featuring every combination of all inputs to any one of the 8 product term (OR) inputs. You should have no problems creating very complex address schemes using a 20V8 device, or a 22V10 for that matter.

Edit: Which you already knew as I could see from the source code. Never mind my comment

/Pontus

Actually, that's what I thought too. However, I discovered the limitations when I was trying to build a simple 13 input NAND gate on a 16V8 chip. I could only do 8 inputs before the compiler gave me errors. I had though that you could AND any and all inputs on a single product term input to an output but the software errors on anything over the product term limit for the output used. The 16V8 and 20V8 have 8 product terms-per-output. The 22V10 has more, ranging from 8 to 16. Purhaps its possible to AND more inputs, but the WinCupl software has a limitation. Anyone else have any insight on this?

Daryl

HiassofT · Post by **HiassofT** » Thu Oct 21, 2010 1:10 pm

8BIT wrote:

However, I discovered the limitations when I was trying to build a simple 13 input NAND gate on a 16V8 chip. I could only do 8 inputs before the compiler gave me errors. I had though that you could AND any and all inputs on a single product term input to an output but the software errors on anything over the product term limit for the output used. The 16V8 and 20V8 have 8 product terms-per-output. The 22V10 has more, ranging from 8 to 16. Purhaps its possible to AND more inputs, but the WinCupl software has a limitation. Anyone else have any insight on this?

It could be a problem in WinCupl, I had a similar issue when I once tried to write a similar (single term) GAL logic in VHDL using ispLever. I guess the optimizer thought it'd be better to convert my single, active low output, AND term into multiple OR terms which of course failed. Maybe I could have solved this issue by configuring the optimizer settings, but I didn't try this.

For GAL logic I prefer the good, old PALASM (use chip PALCE16V8 or PALCE22V10 for GALs). So far it worked very reliable - I already had some issues with broken optimizers in other software.

I remember that an older version of WinCupl had problems when you defined an output to be active low, and a friend of mine was using GDSWin which didn't expand terms with parentheses correctly. Both programs assembled the logic without warnings, but the output was completely broken. In these cases I ran the jedec file through "jed2eqn" and immediately saw that the logic wasn't correct...

Another thing to be careful about 16V8s is whether the GAL is configured to registered, complex, or simple mode. Most of the time used complex mode, but you can't use pins 12 and 19 of a 16V8 as inputs in this mode. In simple mode pins 15 and 16 can't be used as input, and in registered mode you have to keep in mind that pin 11 is used as a global /OE for all registered outputs.

So, for example, if you configure the 16V8 to use complex mode, you should be able to create a 16-input NAND terrm, using inputs 1-9, 11 and 13-18 and pins 12 and/or 19 as outputs.

BTW: personally I prefer the 22V10 over the 16V8 as it's a lot more flexible (no simple/complex/registered mode).

Edit: Just tried the 16-input NAND gate with PALASM and it worked (note that pin 12 is defined as active-low output). This is the source code:

Code: Select all

TITLE    simple NAND gate
PATTERN
REVISION 1.0
AUTHOR   Matthias Reichl
COMPANY  HiassofT
DATE     2010/10/21

CHIP  ramdisk  PALCE16V8

;---------------------------------- PIN Declarations ---------------

PIN 1   I1      COMBINATORIAL   ; INPUT
PIN 2   I2      COMBINATORIAL   ; INPUT
PIN 3   I3      COMBINATORIAL   ; INPUT
PIN 4   I4      COMBINATORIAL   ; INPUT
PIN 5   I5      COMBINATORIAL   ; INPUT
PIN 6   I6      COMBINATORIAL   ; INPUT
PIN 7   I7      COMBINATORIAL   ; INPUT
PIN 8   I8      COMBINATORIAL   ; INPUT
PIN 9   I9      COMBINATORIAL   ; INPUT
;PIN 10 GND
PIN 11  I10     COMBINATORIAL   ; INPUT
PIN 12  /OUT    COMBINATORIAL   ; OUTPUT
PIN 13  I11     COMBINATORIAL   ; INPUT
PIN 14  I12     COMBINATORIAL   ; INPUT
PIN 15  I13     COMBINATORIAL   ; INPUT
PIN 16  I14     COMBINATORIAL   ; INPUT
PIN 17  I15     COMBINATORIAL   ; INPUT
PIN 18  I16     COMBINATORIAL   ; INPUT
;PIN 19 unused
;PIN 20 VCC

;----------------------------------- Boolean Equation Segment ------
EQUATIONS

OUT = I1 * I2 * I3 * I4 * /I5 * /I6 * /I7 * /I8 * I9 * I10 * I11 * /I12 * I13 */I14 * I15 * I16

;----------------------------------- Simulation Segment ------------
SIMULATION

And this is the output of jed2eqn:

Code: Select all

; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063)
; Copyright (c) National Semiconductor Corporation 1990-1993
; Disassembled from nand.jed. Date: 10-21-110
;$GALMODE MEDIUM

chip nand GAL16V8

i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 /i11=11 o12=12
f13=13 f14=14 f15=15 f16=16 f17=17 f18=18 o19=19 VCC=20

@ues 0000000000000000
@ptd unused

equations

o19 = gnd
o19.oe = gnd
f18 = gnd
f18.oe = gnd
f17 = gnd
f17.oe = gnd
f16 = gnd
f16.oe = gnd
f15 = gnd
f15.oe = gnd
f14 = gnd
f14.oe = gnd
f13 = gnd
f13.oe = gnd
/o12 = i2 * i1 * i3 * f18 * i4 * f17 * /i5 * /f16 * /i6 * f15 * /i7 * /f14
      * /i8 * f13 * i9 * /i11
o12.oe = vcc

so long,

Hias

8BIT · Post by **8BIT** » Thu Oct 21, 2010 2:02 pm

Excellent description - thank you very much. I'll do some more research and testing. Thanks also for the software titles - I at least have some alternatives.

Daryl

8BIT · Post by **8BIT** » Fri Oct 22, 2010 5:34 am

For anyone curious about these GAL devices, I would like to clear up a misconception I have created.

I while back, I was asked to come up with a 13 input NOR gate. I thought the 16V8 would work but when I coded it, I got an "too many product terms" error. When I looked into the datasheet, I saw that the 16V8 can support 8 product terms per output.

My code looked like this:

Code: Select all

NOR =  !(I1 # I2 # I3 . . . # I13);

Where ! equals NOT  and # is logical OR.

This is where my misconception started. A product term is an input to an OR gate within the output logic. There for, each output can have up to 8 products OR'd together. A NOR would just send the inverted output to the pin. Thus, trying to OR more than 8 inputs causes an error. However, each product term is actually the PRODUCT of any input or its compliment ANDed to any other. In other words - each of the 16 inputs and its compliment, or 32 lines total - can be ANDed into a single product term.

This is what PontusO was trying to communicate.

So, I went back to the original 13 input NOR requirement and applied a simple logic rule.
NOR = AND with complimented inputs.

It looks like this on a truth table:

Code: Select all

 Input  | Output  |    Input  | Output    
 A   B  |  NOR    |   !A  !B  |  AND
------------------------------------- 
 0   0  |   1     |    1   1  |   1
 0   1  |   0     |    1   0  |   0
 1   0  |   0     |    0   1  |   0
 1   1  |   0     |    0   0  |   0

So, if I modify my original code to use the AND function, I get:

Code: Select all

NOR = !I1 & !I2 & !I3 . . . & !I13;

Where & equals logical AND.

Now I can support a 13 input NOR gate on the 16V8. And I will also be able to support the DEC-1 memory decoder in a 20V8, as Lee originally suggested.

I hope this little tutorial has cleared things up and perhaps sparked some interest in these simple programmable logic circuits.

My thanks to Pontus, Lee, and Hias for their help!

Daryl

BigDumbDinosaur · Post by **BigDumbDinosaur** » Fri Oct 22, 2010 8:22 pm

8BIT wrote:

I have completed development for the 22V10 memory decoder, now named DEC-1.

I plan to revamp my website in the next week or so, but in the mean time, here is a zip file with the source, object, and docs I have compiled.

thanks

Daryl

How did you get the simulation to work? I've yet to be able to get that part of WINCUPL running. I even tried it with your .PLD file and kept getting errors.

8BIT · Post by **8BIT** » Fri Oct 22, 2010 9:23 pm

I had similar problems when I started out with WinCUPL too. You have to create the .si file for the sim to work. I'll try to write up a step-by-step tutorial this evening or tomorrow.

Daryl

BigDumbDinosaur · Post by **BigDumbDinosaur** » Sat Oct 23, 2010 12:11 am

8BIT wrote:

I had similar problems when I started out with WinCUPL too. You have to create the .si file for the sim to work. I'll try to write up a step-by-step tutorial this evening or tomorrow.

Daryl

I figured it out.

8BIT · Post by **8BIT** » Sat Oct 23, 2010 12:57 am

Glad to hear it!

BigDumbDinosaur · Post by **BigDumbDinosaur** » Sat Oct 23, 2010 4:35 am

Just for grins, I hammered out and SIMMed the following PLD code. It is targeted for GAL22V10 devices:

Code: Select all

/*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*                                                                             *
*                   SIMPLE RAM, ROM & I/O DECODING PLD SOURCE                 *
*                                                                             *
* --------------------------------------------------------------------------- *
*     Copyright (C)2010 by BCS Technology Limited.   All rights reserved.     *
*                                                                             * 
* Permission is hereby granted to copy and redistribute this software,  prov- *
* ided this copyright notice remains in the source code & proper  attribution *
* is given.   Any redistribution, regardless of form, must be at no charge to *
* the end user.   This code MAY NOT be incorporated into any package intended *
* for sale unless written permission has been given by the copyright holder.  *
*                                                                             *
* THERE IS NO WARRANTY OF ANY KIND WITH THIS SOFTWARE.   The user assumes all *
* risk in connection with the incorporation of this software into any system. *
*                                                                             *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

* * * * * * * * * *
* VERSION HISTORY *
* * * * * * * * * *

Ver  Rev Date    Revision
-------------------------------------------------------------------------------
 01  2010/10/15  Original version.
-------------------------------------------------------------------------------


MEMORY MAP -- works with W65C02S or W65C816S:

    -----------------------------
    $000000 - $00CFFF   RAM (52K)
    $00D000 - $00DFFF   I/O (4k):

        $00D000    I/O device A
        $00D100    I/O device B
        $00D200    I/O device C
        $00D300    I/O device D

    $00E000 - $00FFFF   ROM (8K)
    -----------------------------


REQUIRED INPUTS:

    Sig   Meaning
    ----------------------------------------
    PHI2  MPU Phase 2 clock
    RWB   MPU read/write data
    VDA   '816 only, pull up to Vcc for 'C02
    VPA   '816 only, pull down for 'C02
    A8    MPU address bus
    A9    MPU address bus
    A12   MPU address bus
    A13   MPU address bus
    A14   MPU address bus
    A15   MPU address bus
    ----------------------------------------


GENERATED OUTPUTS (active low):

    Sig   Meaning
    ------------------
    EPCE  ROM enable
    SRCE  RAM enable
    RD    read data
    WD    write data
    IOA   I/O device A
    IOB   I/O device B
    IOC   I/O device C
    IOD   I/O device D
    ------------------
*/


/*
* * * * * * * * *
* START OF CODE *
* * * * * * * * *
*/

Name      POC V2.0 Memory Decoder;
PartNo    B010150001;
Date      2010/10/15;
Revision  01;
Designer  BigDumbDinosaur;
Company   BCS Technology Limited;
Assembly  POC V2.0;
Location  Ux;
Device    g22v10;


/*
* * * * * * * * * * * *
* INPUT  DECLARATIONS *
* * * * * * * * * * * *

           GAL22V10
          ---------
    PHI2 |1      24| Vcc
    RWB  |2      23|
    VDA  |3      22|
    VPA  |4      21|
    A15  |5      20|
    A14  |6      19|
    A13  |7      18|
    A12  |8      17|
    N/C  |9      16|
    A9   |10     15| N/C
    A8   |11     14| N/C
    Gnd  |12     13| N/C
          ---------

    Pins designated N/C should be grounded to avoid noise problems.
*/

pin 1  = PHI2;
pin 2  = RWB;
pin 3  = VDA;
pin 4  = VPA;
pin 5  = A15;
pin 6  = A14;
pin 7  = A13;
pin 8  = A12;
pin 10 = A9;
pin 11 = A8;

/*
* * * * * * * * * * * *
* OUTPUT DECLARATIONS *
* * * * * * * * * * * *

          ---------
         |1      24|
         |2      23| IOA
         |3      22| IOB
         |4      21| IOC
         |5      20| IOD
         |6      19| WD
         |7      18| RD
         |8      17| SRCE
     N/C |9      16| EPCE
         |10     15| N/C
         |11     14| N/C
         |12     13| N/C
          ---------

    All outputs are low true.  RD is the inversion of the MPU's RWB output & should
    be used to activate the "output enable" input on commonly used RAM, ROM & I/O
    devices.

    Pins designated N/C should be grounded to avoid noise problems.
*/

pin 16 = !EPCE;
pin 17 = !SRCE;
pin 18 = !RD;
pin 19 = !WD;
pin 20 = !IOD;
pin 21 = !IOC;
pin 22 = !IOB;
pin 23 = !IOA;


/*
* * * * * * * * * * * *
* INTERMEDIATE  TERMS *
* * * * * * * * * * * *
*/

cxxx  = A15 & A14;                         /* addr > $00BFFF */
ioblk = cxxx & (!A13 & A12);               /* I/O block address range */
eprom = cxxx & !ioblk;                     /* ROM address range */
vadr  = VDA & !VPA;                        /* valid address qualification */
iosel = ioblk & vadr;                      /* I/O select qualification */


/*
* * * * * * * * * * * * * *
* MEMORY  SELECTION LOGIC *
* * * * * * * * * * * * * *
*/

EPCE  = eprom & RWB;                       /* ROM select (read only) */
SRCE  = !ioblk & !eprom;                   /* RAM select */


/*
* * * * * * * * * * * * * * * *
* I/O DEVICE  SELECTION LOGIC *
* * * * * * * * * * * * * * * *
*/

IOA   = iosel & !A8 & !A9;                 /* I/O device A select */
IOB   = iosel & A8 & !A9;                  /* I/O device B select */
IOC   = iosel & !A8 & A9;                  /* I/O device C select */
IOD   = iosel & A8 & A9;                   /* I/O device D select */


/*
* * * * * * * * * * * * * * * * *
* READ/WRITE  SIGNAL GENERATION *
* * * * * * * * * * * * * * * * *
*/

RD    = RWB;                               /* read data */
WD    = !RWB & PHI2;                       /* write data, qualified by PHI2 clock */

Compile this code in WINCUPL.

The above is slated to be used in my next POC unit, which will also be fitted with a SCSI ASIC. This code includes I/O device select qualification with the VDA and VPA signals from the W65C816S to prevent I/O anomalies when ABS,X addressing is used to talk to chip registers.

The /RD output is the inversion of RWB and the /WD output is the qualification of RWB when low with Ø2 when it is high.

I have tested this in the WINCUPL simulator and all valid input combinations work as expected.

If you want to use this in-circuit, you should connect the /RD signal to the /OE inputs on RAM, ROM and I/O hardware. Doing so will automatically account for those cases where /OE and /WE (write enable) should not be simultaneously asserted. /WD should go to the /WE input on RAM and I/O hardware. Note that I/O hardware is only selected when the appropriate VDA and VPA combination is present with the W65C816S. See notes in the code about what to do with those inputs when using this with a W65C02S.

In a (near) future enhancement, I'm going to see about incorporating I/O wait-stating into the device. I've already prototyped a circuit on perf board, so now it's a matter of developing the required code.

BigDumbDinosaur · Post by **BigDumbDinosaur** » Sun Oct 24, 2010 5:27 am

You can view the simulator display for the above code right here. In this particular run, the address $D000 has been placed on the bus, which means IOA is being selected. Also, at one point there is a write operation to whatever is connected to that signal. Note how the device selection is contingent on VDA being high and VPA being low. Also note that /WD (write data) doesn't go low until Ø2 is high, just as it is supposed to do.

faybs · Post by **faybs** » Sun Oct 24, 2010 9:39 am

Sortof on-topic, is there a reasonable, low cost PAL/GAL/PEEL burner that the pros here would recommend? preferably one that doesn't require a parallel port. It doesn't need to support whiz-bang Xilinx and Altera devices, just the simple PLDs that one would use to replace a handful of TTL chips for glue logic (eg Daryl's DEC-1). I've been looking around, but I don't know enough to tell the difference between a good deal and cheap junk. I'm pretty sure the $1000 gizmos are all good quality, but that's a tad above what I'm willing to spend

8BIT · Post by **8BIT** » Sun Oct 24, 2010 3:25 pm

I am using a Genius NSP which is an older model that can program EPROM's, a few microcontrollers, and Lattice, 16V8, 20V8 (untested), and 22V10 GALs. It uses an RS-232 connection ot the PC.

The current model is the G540. You can find them on Ebay for $46 + $25 shipping from Hong Kong. They are USB connected to the PC and use Windows software. Tech support is not available.

There is also a top853 model on Ebay for $50 which looks like a very similar item that states it supports Atmel and Lattice GALs.

The Willem programmers are supposed to be very flexible but I have not researched them. Their cost is ~$40 on ebay so they may be worth looking into. I think one of our members has one, if I recall. The one I saw on Ebay did not list GAL devices but I asked the seller about them. If he responds yes, I'll post that back here.

Daryl

BigDumbDinosaur · Post by **BigDumbDinosaur** » Sun Oct 24, 2010 7:29 pm

faybs wrote:

Sortof on-topic, is there a reasonable, low cost PAL/GAL/PEEL burner that the pros here would recommend? preferably one that doesn't require a parallel port. It doesn't need to support whiz-bang Xilinx and Altera devices, just the simple PLDs that one would use to replace a handful of TTL chips for glue logic (eg Daryl's DEC-1). I've been looking around, but I don't know enough to tell the difference between a good deal and cheap junk. I'm pretty sure the $1000 gizmos are all good quality, but that's a tad above what I'm willing to spend

There are several available from eBay sources. The el cheapo one I use for this sort of stuff is a TOP853, which connects to a PC via USB and is able to program EPROMs, EEPROMs, various PLDs, etc. I've used it to burn EPROMs for my POC unit, and it seems to work just fine. You'll get a chuckle or two from the Chinese to English translations in the software.

faybs · Post by **faybs** » Sun Oct 24, 2010 9:13 pm

Thanks guys. From my research Willem programmers don't work with PALs or GALs (some work with Altera and Xilinx CPLDs using a JTAG cable, but I expect to very rarely, if ever, use those). I'll look into the TOP853.

HiassofT · Post by **HiassofT** » Mon Oct 25, 2010 11:06 pm

BigDumbDinosaur wrote:

The el cheapo one I use for this sort of stuff is a TOP853, which connects to a PC via USB and is able to program EPROMs, EEPROMs, various PLDs, etc. I've used it to burn EPROMs for my POC unit, and it seems to work just fine. You'll get a chuckle or two from the Chinese to English translations in the software. :)

Which software version are you using and have you tried to program a (Lattice) GAL 22V10 with it?

I just bought a top2004 and noticed that programming 22V10 GALs is broken in topwin 2.x and 3.x (the only versions supporting the top2004 - topwin 5.x always says "no chip selected" and 6.x doesn't recognize my programmer).

BTW: the topwin software doesn't seem to support GAL vector tests, a really nice feature that I often used with my old Xeltek SuperPro.

Well, you get what you pay for...

so long,

Hias

Simple Memory Decoder GAL

WINCUPL Simulation

Decoding GAL Part II

Decoding GAL Part III

Burn baby! Burn!

Re: Burn baby! Burn!