Not intentionally hijacking this thread but... I've already figured out my clocks for EEPROM copy/ SRAM run modes, 1 fast & one slow, no variable frequency needed. I'm just trying to make my digital pulse width analyzer more useful than just analyzing automotive injectors, typically 500uS to 4mS on an 8 cyl engine. Not too much speed or even variation in desired clocks needed to clock 16 bit counters. These CPLDs are capable of 80+ MHz with what I've programmed them for....
Despite this, I have always been intrigued by digitally controlled clock generation, but PLLs were always above my understanding. I used to look at a CD4046 datasheet, I still remember the part # without looking it up!, and think how do I really make this thing work?!
ChuckT, there's a simple circuit I made here with a VCO good to many MHz above the 6502 capability, using a 74S124. It does get hot though, which means it is using quite abit of current (I think about 100mA). It does the job done for benching/prototyping with abit of jitter although it has not interfered with software execution @~10MHz.
9th post from the bottom.
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-EyE