SMT/SMD, 3V3, and CPLD Routing Tips?

[SamCoVT]

sburrow wrote:

I went and looked up the TI version, TLV1117LV33, and yep that datasheet has a lot more information. Thank you for telling me about this.

I just noticed that you used the TLV part here - that's a low voltage part that only accepts 5.5V max as input. It will work for your application, but if you have extras then you won't be able to use them for 9V or 12V down to 3.3V applications later.

The part number I was referring to when I said "TI's datasheet" is the LM1117IMPX-3.3/NOPB available here. The LM is National Semiconductor's prefix, but TI bought them a while ago. The datasheet for TI's LM1117 is the one with the extensive thermal section (9.5.1.1 Heat Sink Requirements) that is worth reading. The TLV version doesn't have this section.

[sburrow]

SamCoVT wrote:

The part number I was referring to when I said "TI's datasheet" is the LM1117IMPX-3.3/NOPB available here.

Haha, well I feel like I'm going full circle here. I had originally used an LM1117-3.3 on a different project, but in a different package. It is true I do not need more than 5V input, as this is designed to be connected to a SBC which wouldn't be supplied with more than 5V anyways. I don't think anybody *runs* a 6502 at 12V, right?

SamCoVT wrote:

It looks like the 1117 family should be OK with you powering up the 3.3V side directly as long as you don't short the 5V (input) side to ground. I would expect you would leave the 5V (input) side floating when you are not using it.

Where did you find this information? So that, in the future, I know where to look for it?

Thank you so much Sam, you have been so very helpful, and I have been learning a great deal from you! Good math calculations. So, again, thank you. This has been a great learning experience.

Chad

[SamCoVT]

sburrow wrote:

SamCoVT wrote:

It looks like the 1117 family should be OK with you powering up the 3.3V side directly as long as you don't short the 5V (input) side to ground. I would expect you would leave the 5V (input) side floating when you are not using it.

Where did you find this information? So that, in the future, I know where to look for it?

Section 8.4.1 of the TI datasheet titled "Protection Diodes". If you read the couple of paragraphs there, you will find that there is already a diode between Vout and Vin (meaning that if you inject 3.3V into the 3.3V rail, the Vin pin will be a diode drop lower than that, so around 2.6-2.7V. It won't be regulating, obviously, but it also won't damage the internal diode as long as the input is not shorted to ground. The datasheet claims that surge currents of 10-20A can flow through this diode as long as they are microsecond in duration. That would be an argument for not having too large of an INPUT cap, which would appear like a short to ground until it charges up. The 10uF input and 10uF output tantalum caps recommended in section 9.2.2.1 "External Capacitors" are likely to be fine and should not create currents that high.

I recommend reading all of sections 8 "Detailed Description" and 9 "Application and Implementation" in this datasheet. It's 11 pages but most is schematics and charts so it's only about 4 pages of reading. I will note that Figures 9-17 and 9-18 appear to have TOP and BOTTOM reversed (even TI makes mistakes). Once you've read through that, you should be able to make all the design decisions around this device and have a general feel for "is this design good enough". It doesn't need to be the best - it doesn't even need to be all that good - it just needs to be good enough that you don't need to think about it much any more and can focus on the rest of your design.

For what you are planning to use this for, you are unlikely to need to know anything more about this device. For analog work, you might be concerned with things like line and load regulation, ripple regulation or rejection, output deviation over temperature, etc, but for digital logic, a lot of that doesn't matter (until you have a problem where it does, of course, and you can learn about it then).

[Arlet]

I don't agree with the advice on copper fills. I use them all the time. On a 2-layer board, I do a GND fill on both sides, and then provide plenty of vias to connect them. Track and spacing are set to minimum, and vias are used liberally to avoid long continuous traces that chop up the fills. Buses of like signals run closely parallel, maximizing area around them for the copper fills. On 4 or 6 layer boards, I usually do one layer with VCC, and all remaining layers with GND. I've made several boards with signals running at 100+ MHz, and never had a problem with signal integrity.

[Dr Jefyll]

Arlet wrote:

I don't agree with the advice on copper fills. I use them all the time. On a 2-layer board, I do a GND fill on both sides, and then provide plenty of vias to connect them. Track and spacing are set to minimum, and vias are used liberally to avoid long continuous traces that chop up the fills.

Is there a terminology problem? This might explain some needless controversy and confusion about fills aka pours.

To me, the word fill or pour implies a copper area that's only very casually connected to ground (for example, it might be grounded at only a single point). So, it's readily capable of acting as an electrostatic shield -- which may be helpful in audio work, for example -- but for digital signals it's desirable to provide return paths that can carry current between the Gnd pins of various IC's... and a copper area that's grounded at only a single point obviously cannot carry current between IC's.

But you've twice mentioned plenty of vias, presumably to Gnd, and from that I infer that your goal is to carry return current.

It would be nice if we had a new word to describe this. Although your system of distributed, interconnected grounds falls short of being a true ground plane, it has a lot in common with a ground plane... and little or nothing in common with a fill (according to my interpretation of that word).

-- Jeff

[Arlet]

In my understanding, a fill is simply a big polygon filled with copper that's connected to a specific net. In the case of ground fills, it's usually the same shape as the board outline.

Quote:

But you've twice mentioned plenty of vias, presumably to Gnd, and I infer that your goal is to carry return current.

Indeed. It is meant to be a substitute for a ground plane. In addition to adding plenty of vias, I keep an eye on the overall "flow" and try to avoid isolated islands. A useful tool is to highlight the ground, so you can see where it flows.

In case of 4+ layer boards, I usually try to make 1 completely clean ground plane, but I still fill all other open spaces with ground, and add similar kinds of vias to connect it all together. The added bonus is that the different layers have very similar copper density which gives a nice even plating index, improves thermal properties, and prevents board warping.

It's also very helpful to make thin (0.15 mm/6 mil) signal traces and clearance, and keep similar signals (like address/data buses) closely parallel to minimize board clutter.

[GARTHWILSON]

Arlet wrote:

In my understanding, a fill is simply a big polygon filled with copper that's connected to a specific net. In the case of ground fills, it's usually the same shape as the board outline.

That's a ground plane.  By "fills" or "pours," we're talking about filling smaller blank areas here and there on the board, which is usually done by people who think it's about electrostatic shielding and don't understand the matter of mutual inductance and a ground return that needs to be continuous under the signal trace it's returning the current for, for the entire length, without interruptions or detours.

Quote:

I keep an eye on the overall "flow" and try to avoid isolated islands.

Right.  Isolated islands are a problem when used as a substitute for a ground plane.  If they are done right, they can augment a true ground plane, but if not done right, they can actually hurt performance, even if there is a ground plane.  This is according to the lectures from the industry gurus Eric Bogatin, Susy Webb, Rick Hartley, and others, linked at the end of my AC performance page at http://wilsonminesco.com/6502primer/construction.html .

[sburrow]

Well, I've been experimenting! And now I have some questions about interacting with 3.3V.

1) My 3V3 CPLD is sending address signals to my SST39SF040 Flash ROM. The ROM is powered by 5V. I have looked over the datasheet and I cannot find anywhere it says that 3V3 inputs are acceptable except for a tiny mention "TTL compatible". Right now I have 3.3K pull-up resistors to 5V on those lines so (in theory) the 3V3 signal from the CPLD is simply grounding when low and 'letting the resistors pull up' when high. At least that's my theory. I believe it still works without those resistors but I'm scared to touch this ... breadboard. I am aware of the SST39LF040, powered by 3V3, but it also says it's "max high input" is not 5V, so it doesn't seem 5V tolerant. Any experience with the SST39SF040 with 3V3?

2) My 3V3 CPLD is connected to a 74HC166, with 1K pull-up resistors to 5V, and it seems to work ok. When I didn't have those pull-up resistors I got interesting results at times. I plan on replacing it with a 74HCT166. That should be seamless, right? No need for pull-ups anymore?

3) I'm sending a 5V signal to my 3V3 CPLD. The CPLD is the XC9572, which is 5V tolerant. But I was reading the high and low logic levels for it on the datasheet. A high is anywhere from 2.0 to 5.5V, but a low is 0 to 0.8V. I think this ... breadboard is giving me groundbounce, perhaps past the 0.8V range, and so I put a 1K pull-down resistor on the 5V signal to stabilize it. It works much better with it there, and works sometimes without it. Does this sound right to you?

Any thoughts are much appreciated. Thank you all!

Chad

[Martin A]

The VIH figure from the DC part of the datasheet shows you the minimum voltage that will be accepted as a high, in this case that's 2.0v. There's no maximum quoted so anything from 2v to the absolute maximum of any pin of VDD+0.5 is acceptable. (Though input voltages over the supply should be avoided for the long term health of the device.)

As long as the CPLD is guaranteed to output at least 2v, then you're in spec.

Datasheet snip

[sburrow]

Martin A wrote:

The VIH figure from the DC part of the datasheet shows you the minimum voltage that will be accepted as a high, in this case that's 2.0v. There's no maximum quoted so anything from 2v to the absolute maximum of any pin of VDD+0.5 is acceptable. (Though input voltages over the supply should be avoided for the long term health of the device.)

As long as the CPLD is guaranteed to output at least 2v, then you're in spec.

SST VIH.jpg

Thank you, and yes I saw that.

But the "CMOS" version does not guarantee 2.0V. So what is the difference between the CMOS and the, uh, blank?

Thank you again.

Chad

[sburrow]

I've been designing the 4-layer board, and I came across an interesting predicament. Attached are pictures.

This is a SOIC-16 chip. As you can see, I am using vias to bring the 5V and GND signals to their inner layers. I am not putting the vias *on* the pads, but very near it. But the via for 5V is in between the bypass cap and the pin. This saves a lot of room! But I have a feeling like it's not optimum. If it is not optimum, is it still "good enough"?

Thank you for any insight.

Chad

[Proxy]

At the kinds of speeds these systems run at, even using an autorouter is "good enough" most of the time.
So I'm sure what you're doing there is fine.

[plasmo]

It is common to place bypass caps at back of the components. Like Proxy has said, reasonable placement then auto route is good enough. You’ll find with 4-layer pcb, the design is most likely functional without any bypass cap. During product qualification we may build up a qualification unit without any bypass cap to check system noise margin. In most cases such qual units worked just fine.
Bill

[SamCoVT]

sburrow wrote:

I am not putting the vias *on* the pads, but very near it. But the via for 5V is in between the bypass cap and the pin.

This looks fine to me. When you get into the hundreds of MHz and GHz ranges, then exactly where you place things matters a lot more, but at the speeds this board will run at (tens of MHz) it's probably not going to matter that much and what you have looks better than average (meaning you have a very high chance of it being just fine).

When designing PCBs, there are always things you can do to make it better, however any given board just needs to be good enough and many things you do to make one thing better can make another thing worse. It also takes time to keep optimizing the board, so it's better to just get to where it is good enough and not waste any more time unless you really need those optimizations.

Is your design good enough? Very likely. You've even followed some best practices like using power/ground planes, using SMT caps, placing the cap very close to the IC, and placing the vias close to the cap; you are already well above the "good enough" level. Any further optimizations you might do, such as actual location of the vias or how many you use to connect to the power/ground planes, aren't going to have much effect at your speeds and power levels and probably not worth spending time on. As Bill notes, your circuit might even work without any bypass caps installed (but you should install them, as they make things measurably better).

[Arlet]

For hand soldering, or home reflowing in a toaster oven, it's not a problem to put a via inside a pad. It will suck up some solder, but you can always fix that.