Design challenge: 6502-based EPROM programmer

For discussing the 65xx hardware itself or electronics projects.
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Sheep64
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Re: Design challenge: 6502-based EPROM programmer

Post by Sheep64 »

Sheep64 on Thu 11 Nov 2021 wrote:
You're probably over-thinking this problem.
No, actually, I'm under-thinking the problem. The shift register solution requires four signal lines: clock, data, set bits live - and then a programming pulse with controlled duration. I considered bodging this into a NES input peripheral extension. However, that would be a horrible exercise. For a more elegant solution, I highly recommend AndersNielsen's scheme to de-couple processor speed and pulse width by using a crystal clocked shift register which deliberately runs dry. AndersNielsen devised this to control WS2812B LEDs from 2MHz 6502 but the principle is widely applicable.

XR2801 is an attempt to implement a shift register design. I'm beginning to understand that circuit board layout is an iterative annealing process where the first attempt is best discarded. Even after several iterations, there may be WTF design decisions which can be optimized; most typically wires to nowhere, curious junctions (which look great on screen) or scenic tours around a board.

My first attempt was entertainingly awful. I "painted myself into a corner" where I required a fly lead to continue the shift register chain. In mention this because experienced designers may be amused by my first encounter with this phenomena. Likewise, I was unhappy with a power, clock and serial data bus which ran around the edge. I was more disappointed by component orientation. In an draft version of the XR2601 main board, I found that inward DIP components allowed ground around the outside and an inner power rail. However, this is only useful is very specific circumstances and is deprecated on all designs. I can almost feel BigEd's stern, tutting disapproval of my willful violation of least surprise. (In this and other matters, I am considerably swayed by BigEd's advice.) However, this was not the most disappointing feature of my design. A design of this triviality should not have 10 vias.

I repeated the design with a more suitable data path. I also ensured that the two most popular EEPROM types can be programmed. Oddly, this didn't make the design wider. It only made the design taller to accommodate 28 pin DIP and 32 pin DIP chips. The discussion about "river routing" aided one tight spot. Overall, I am happy that I got a superior design down to one via.

I am working on a list of design rules and this redundant newbie exercise has been helpful to refine the list. In particular, I specify large (3mm tall, 0.3mm thick) silk-screen component numbers on both sides of the board. Likewise, interface signals are silk-screened on both sides. I am similarly fastidious about fixing holes and rounded corners. I am my primary customer and I am able to describe in vast detail how my primary customer is not only an idiot but an award winning idiot. This is particularly true before a second coffee. Therefore, skimping on safeguards will disproportionately disadvantage myself.

My overall intention is that any module may be soldered, interfaced, affixed and programmed without reference to documentation. Obviously, this is impossible in most cases. However, I believe that it is highly beneficial to streamline the process wherever possible. Unlike software comments which may fall out of step, text on a board must be current otherwise it will be mis-leading or contradictory. Sheep20 is amused by my placement of text typically of the form "SOLDER GOES ON THIS SIDE. COMPONENTS GO ON OTHER SIDE." and is particularly amused by abbreviated versions on smaller boards, such as "CHIPS THIS SIDE" or "CHIP SIDE", and suggested that we might be mistaken for a venture called Chipside Technology or similar. Actually, that could be a plausible Taiwanese name and it wouldn't look out of place among Allwinner, Ainol or Award. Nor would it look out of place among CkeyiN®, Dttrol or Xiomi.

I highly recommend designing your own EEPROM programmer. Although it has been done thousands of times before, it is a good exercise and oddly satisfying. However, if you are in a hurry, an untested example is freely available.
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plasmo
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Re: Design challenge: 6502-based EPROM programmer

Post by plasmo »

Ah, that reminds me. Prog65 is finished and documented here:
https://www.retrobrewcomputers.org/doku ... og65r2home

I still have 4 extra pc boards. Anyone (in USA) interested, please PM me with your addresses. I'll ship a bare PC board in First Class letter mail free.
Bill
Prog65_rev1_f.jpg
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GARTHWILSON
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Re: Design challenge: 6502-based EPROM programmer

Post by GARTHWILSON »

FWIW, I just started a related topic, "(E)EPROM/flash programming algorithms.
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
plasmo
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Re: Design challenge: 6502-based EPROM programmer

Post by plasmo »

I'm reviving this thread because of couple interesting recent topics:

overclocking DIP 6502 with TTL logic, viewtopic.php?f=4&t=7670
locked room challenge, viewtopic.php?f=4&t=7686

Prog65 is based on DIP 6502 using TTL logic so I'm curious whether it can be overclocked into mid-20MHz, specifically 25.175MHz which leads to the "locked room challenge" because at 25.175MHz 6502 can beam race VGA display with the help of a parallel-load 8-bit shift register, 74166, thus serves as a VGA monitor. Prog65 can bootstrap itself through the parallel interface to program a new flash so it may be possible to create dual-6502 standalone computer from scratch as stipulated in the "locked room challenge".

To run at 25.175MHz, I need fast RAM. My existing DIP RAM is 55nS and I need 20nS RAM which I do have but it is in 32pin SOJ package. First modification is to wire in the SOJ32 RAM instead of the DIP RAM. This is done at the back of the board using point-to-point wiring to minimize wire length. Pictures of the modified Prog65.
prog65_fastRAM_top_F.jpg
Prog65_fastRAM_bottom_F.jpg
It works at the nominal 7.37MHz but intermittently crashed at 10MHz, so no hope of getting it to run at 25MHz without logic modifications. Prog65 has nice breadboard area for adding logic so the idea is to add one wait state for flash and I/O at $8000-$FFFF but keep RAM access ($0-$7FFF) at zero wait. Prog65 is an auto-routed 2-layer PC board so it is not clear how fast I can overclock it.

To be continued...
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Michael
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Re: Design challenge: 6502-based EPROM programmer

Post by Michael »

plasmo wrote:
To run at 25.175MHz, I need fast RAM. My existing DIP RAM is 55nS and I need 20nS RAM which I do have but it is in 32pin SOJ package.
Might these relatively inexpensive 10/15/20-nS skinny 64K RAM chips be useful? I suspect they're 'pulls' but they're very clean and I haven't had any problems with them, so far.
W24512AK.jpg
The RAM chips are inexpensive enough at ~68¢ each that I don't mind soldering them directly onto a PCB underneath the CPU.
SBC6502 proto zif.png
BTW, I also made a small 0.8-mm thick PCB with a 64K RAM chip that fits onto the shoulder of the pins on a 40-pin machined pin socket intended for a 6502 CPU that might be used to simplify PCB routing and reduce board space. You could solder the socket with integrated RAM directly onto a PCB or place it in-between a CPU and existing CPU socket (I'd be happy to send you a PCB, if you'd like).
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6502 Socket.jpg
Last edited by Michael on Fri Aug 04, 2023 5:12 am, edited 1 time in total.
plasmo
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Re: Design challenge: 6502-based EPROM programmer

Post by plasmo »

I think the fast skinny DIP RAM is very nice and cheap. It can be tucked under flash or CPU as you’ve done. I’ve a roll of SMT 128K RAM, that’s why I used it extensively. I’ve made an DIP-SMT adapter (https://www.retrobrewcomputers.org/doku ... rds:no-ps2) but I’m out of the adapter that’s why I manually wired one for this experiment.
Bill
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Michael
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Re: Design challenge: 6502-based EPROM programmer

Post by Michael »

Just thought I'd mention it as a simple low-profile solution. I thought about using the method for a mini' SBC by stacking sockets (see below).

BTW, that AliExpress vendor also sells 15-nS skinny 128K RAM chips for the same price (about 68¢ each).

Good luck on your project...
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1802 Stack.png
barnacle
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Re: Design challenge: 6502-based EPROM programmer

Post by barnacle »

I still remember the shock we felt back in the early eighties when we discovered that the Ikegami HL-79 [0] portable TV camera had the never-before-seen concepts of ICs on both sides of the boards...

Neil

[0] Handy Looky - really, so of course the tech manual was instantly christened the Handy Looky Cooky Booky
plasmo
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Re: Design challenge: 6502-based EPROM programmer

Post by plasmo »

I was hoping to preserve the programmer mode of operation while adding a wait state to $8000-$FFFF, but it didn't work out with the limited TTL logic available on the original Prog65 board. I'm reluctant to add too many gates because it'll only slow down the overall operation. So I only bodge a 74ACT74 to add one wait state for accessing $8000-$FFFF where FT245 console I/O and flash memory are located. This is the old-fashion delay-RDY-by-one-clock approach, not the clock-stretch approach. Flash (SST39SF010) is rated at 70nS so with one wait state, the calculated max clock is 20MHz. With small mods, the flash socket can also accommodate 45nS W27C512 which is good to 33MHz.

My test program is the simple four-function monitor that loads file, execute file, display memory and modify memory. The monitor resides in flash from $F000 to $FFFF.

Good thing about FT245 is its communication is independence of CPU clock, so I can change 6502 clock arbitrarily without worrying about its effect on console communication.

Below is the modified Prog65 and associated schematic. I want to minimize the cut/jumper to existing design so the modification is not as efficient as starting with a brand new design.

The bottom line is the modified Prog65 can run to 24MHz with 70nS SST39SF010. This is because SST39SF040's access time is conservative allowing it to work at about 55nS. In fact, SST39SF010 partly worked at 25MHz, successfully display/modify memory and execute program at specified location, but the file load operation failed checksum check. Further investigation showed flash was not the bottle neck; using faster W27C512 I can run to 28.8MHz as verified by scope but I/O communication were gibberish. The bottle neck turned out to be FT245. The FT245 interface has several cascaded gates thus introducing significant timing skew. Perhaps 74AS27 may help; or perhaps I should have 2 wait states for flash and I/O.

At this point 25.175MHz operation is tantalizingly close. DIP 6502 and 2-layer PCB have not being limiting factors.
Bill
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prog65_overclock_experiment_top.jpg
gfoot
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Re: Design challenge: 6502-based EPROM programmer

Post by gfoot »

Bill your point to point soldering is very impressive to me, it's a skill I've pretty much given up on learning, as my attempts so far have been so bad and frustrating. I can do through hole and SMT, but I just don't seem to have the coordination to hold tiny springy wires in place while I solder them!
plasmo
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Re: Design challenge: 6502-based EPROM programmer

Post by plasmo »

I use medium tip tweezers to bend 30-ga wire to a hook then reflow the solder while pulling the hook into reflowed solder. Once one end of a wire is soldered, the other end is easier to manipulate and solder. It is not as fast as wire wrapping, but fast enough to do small prototype. I have good set of wire wrap tools including an electric wire wrapper, but have not use them for last 10+ years.
Bill
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