Hi,

Does anyone know if there is any latency (even half a cycle) in pulling nIRQ high when a timer interrupt is acknowledged (either by reading T1C-L/T2C-L or by writing T1C-H/T2C-H)?

I'm trying to do a very accurate simulation, specifically to handle a case similar to Garth's "ghost interrupts", in which an IRQ is taken the cycle after a read from T1C-L, even though this read would have acknowledged the IRQ, and it seems to me that the only way this can make sense is if there's some kind of latency.

Supposing T1C-L is at $FE44, here are a couple of Visual6502 simulations of an IRQ being generated while reading from $FE44:

• In this first case, the interrupt is acknowledged at the last possible moment that would stop the interrupt from being taken.
• In this second case, the interrupt is acknowledged at the first possible moment that would allow the interrupt to be taken anyway.

If the second case represents more or less what has been observed in the past, this must mean that a cycle passed between T1C-L being read and nIRQ going high. Has anyone ever measured this with a logic analyser, or have any documentation to this effect (I can't see anything in the 6522 datasheet)? Or if not, does my interpretation seem sound there, and is this a reasonable assumption to make? I'm not 100% sure exactly when the read from $FE44 is done, but my best guess is last half of T3?

Anyone here more hardware-inclined than me who can make sense of this?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks Garth!

One thing I don't quite understand is, in your case of ghost interrupts, you said that it happened when an interrupt happened during an instruction to disable that interrupt. Presuming that was a store to the IER, that shouldn't have affected the IFR, so do you mean that in your interrupt service routine you were doing the 'well behaved' thing of LDA IFR / AND IER and using that result, which was consequently yielding nothing? Just trying to understand this weird behaviour properly.

I'm not hardware-minded enough to really understand your explanation of a 'pull-up resistor needing time to charge the capacitance on the line' (I wish I knew where to start ) but I get the idea that it's common that it should take a little time before the line goes high again. In any case, I'm going to go with the model that the 6522 takes at least half a cycle to pull nIRQ high, and see if my simulator yields the same results as real hardware. If not, back to the drawing board...

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

But what will have pulled it in this instance? Still not quite understanding the scenario, but I appreciate that this was ages ago and the details are undoubtedly fuzzy!


That's interesting - do you have any detailed docs on the timing differences between the CMOS and NMOS versions? As we can see from Visual6502 in this somewhat exaggerated example, as long as nIRQ is low during the first half of T0, the interrupt sequence will begin, and this is the only place the CPU checks whether an interrupt should be taken or not. Its level during any other 6502 timing state appears to be irrelevant. Is the 65C02 different in this respect?

Thanks for the analogy. I'm very much a software guy (my current project involves writing a very precise 6502/6522 simulator amongst other things), but I'm interested in trying to understand what's going on underneath it all, and so these little insights are very useful!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Some relatively good simulation can be found in the VICE Commodore emulator, that also emulates the VIC-20 with its dual 6522. And this VIC20 emulator is used for demo coding etc, before going to the real machine, so it should be good.

(... and I put a lot of thought into the VICE CIA and VIA timer emulations back then.... B-)
(but they sure have been improved in the meantime as well)

André

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Ah, that's a great find, thank you for posting that! So according to that, there's absolutely not a delay in pulling nIRQ high after a read from T1C-L, which is a shame as it means I have to come up with another theory as to how these "ghost interrupts" occur I noticed in the full datasheet for the SY6522 that the IRQ\ output is open drain, so it surprises me that the rising edge occurs so quickly, given what you've previously said about how this works. The VIA in the case I'm trying to understand was an R6522AP, but this is more-or-less identical as far as I can tell.

Thanks fachat, I already took a look at VICE, but it seems that these real subtleties of the VIA operation haven't really been described anywhere before, and are really only necessary for absolutely precise simulation.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Ah OK, thanks Garth for the clarification!

Just for the record, I think that branches behave differently - there's a discussion at viewtopic.php?t=1634

Also note that the tabulation in visual6502 has been corrected since some of the prior experiments. We now see that the usual case is that an interrupt input must be low at the start of a T0, normally, or low at the start of a T3, for branches. By "low at the start of" a cycle, I mean "low during the end of the previous cycle".

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Cheers
Ed