Hello,

sorry for interfering. Hope you don't mind. While looking for some information about the 6502, I stumbled across this interesting forum and found your threads about the 65org16 and other related topics. I was truly amazed by the knowledge and experience of the people here and hence their ideas, and I digged through the depth of the threads to gather as much information as possible. And finally at the weekend I sat down and wrote a little experimental 65org16 emulator and assembler to fool around with the opcodes (*) and to get a feeling what programs and programming would be like. As expected a few problems arose, and now I wonder if it were possible to ask you some questions concerning the 65org16/65org32. Well, actually, I would have plenty of questions, so I didn't even know where to post this since the questions include things like emulation as well as programming or ISA design. Feel free, please, to move this post around to another thread if you like. Oh, and this is my first post here. Have mercy on me, please...

Miles

(* right now only the old 65c02 instructions extended to 16 bit without the additional registers)

Thanks! I've got a lot of questions, indeed, but I really don't want to cause any trouble. So, here are just a few:
1) A simple question just to make sure: is the behaviour of the stack instructions PHA, PLA etc and JSR, RTS the same as on the 6502 (PHA = write value then decrement S, PLA = increment S then read value, JSR = increment PC, write high word, decrement S, write low word, decrement S)?
2) How many cycles do the instructions use (relative in comparison to each other)? Just a rough estimate, so that I can adjust the emulator and watch out for bottlenecks in the program.
3) Is the stack placed at $0001 0000 .. $0001 ffff? The IRQ vectors are found at $ffff fffa etc? Is there an additional COP vector ($ffff fff4) or something similar that can be used for system calls?
4) Does a dev. board exist with an attached video generator? If so, how is it organized and what is the resolution? (So I can perhaps emulate some kind of display output.)
5) Would it be possible to add the instruction 'JSR (zp, x)'? This may seem very odd at first, but there's a reason. When I write larger programs I use object oriented programming a lot. In x86 assembly you would likely use something like 'mov eax, [esi + offset]' for loading an object attribute value. On a 68000 there is 'MOVE.L offset(A5), D0'. Unfortunately an addressing mode like 'LDA (zp), #offset' does not exist, and addressing attributes using 'LDY #offset : LDA (zp), y' would result in very long code. So I decided to place the objects into the zero page, load the X register with the address of the object and use the zp value as the constant offset of the attribute. This will give me 'LDA offset, x' for loading the attribute value of an object pointed to by X. So far so good. The problem is: how do you call an object method? The x86 has 'call [esi + offset]' for this. The 68000 at least got 'JSR offset(A5)' in combination with an additional ' JMP abs.L'. All members of the 6502 family lack a short and quick way to perform this call, although it is really very useful and may speed up programs drastically. Now even a zp as the offset would be enough, as the objects reside in zero page anyway. Hence 'JSR (zp, x)' would be fine. What do you think: would it be possible/make sense to add such an instruction?
6) Are there still plans to include instructions for multiplication and division? (I personally would prefer a simple unsigned 'MUL' that multiplies A * Y with the result in Y (low) and A (high) but that's a matter of taste really.)
Now I could go on endlessly, but I rather not get on your nerves if I haven't done so already. Thanks for your patience.

Miles

1) A simple question just to make sure: is the behaviour of the stack instructions PHA, PLA etc and JSR, RTS the same as on the 6502

2) How many cycles do the instructions use (relative in comparison to each other)? Just a rough estimate, so that I can adjust the emulator and watch out for bottlenecks in the program.

3) Is the stack placed at $0001 0000 .. $0001 ffff? The IRQ vectors are found at $ffff fffa etc?

Is there an additional COP vector ($ffff fff4) or something similar that can be used for system calls?

I personally would prefer a simple unsigned 'MUL' that multiplies A * Y [...] Now I could go on endlessly

4) Does a dev. board exist with an attached video generator? If so, how is it organized and what is the resolution? (So I can perhaps emulate some kind of display output.)

5) Would it be possible to add the instruction 'JSR (zp, x)'? [for object methods ... other CPUs have something...] All members of the 6502 family lack a short and quick way to perform this call, although it is really very useful and may speed up programs drastically. Now even a zp as the offset would be enough, as the objects reside in zero page anyway. Hence 'JSR (zp, x)' would be fine. What do you think: would it be possible/make sense to add such an instruction?

6) Are there still plans to include instructions for multiplication and division? (I personally would prefer a simple unsigned 'MUL' that multiplies A * Y with the result in Y (low) and A (high) but that's a matter of taste really.)

That core is, I think, cycle-count accurate with the NMOS 6502 (but swaps some memory accesses around.)

...3) Is the stack placed at $0001 0000 .. $0001 ffff? The IRQ vectors are found at $ffff fffa etc? Is there an additional COP vector ($ffff fff4) or something similar that can be used for system calls?...Miles

...4) Does a dev. board exist with an attached video generator? If so, how is it organized and what is the resolution? (So I can perhaps emulate some kind of display output.)...Miles

...6) Are there still plans to include instructions for multiplication and division? (I personally would prefer a simple unsigned 'MUL' that multiplies A * Y with the result in Y (low) and A (high) but that's a matter of taste really.)
Now I could go on endlessly, but I rather not get on your nerves if I haven't done so already. Thanks for your patience.Miles

A simple MUL can be dropped in, I think. Division seems to be difficult, in the sense that it's a multi-cycle operation and there's no drop-in hardware for it, so that's less likely unless someone pops up. A division-step instruction might be more likely.

So, adding the necessary states to handle JSR (zp, x) isn't something I'm likely to tackle.

The cycle count is identical to the NMOS 6502

The next board I make ..

Please consider posting something in the Introduce Yourself thread

Okay, no problem. For now I will use a little subroutine for division when needed. MUL would be more useful anyway, I guess (e.g. for calculating the pixel address inside a window with arbitrary size).

Thanks for the answers and the links!

Understandable. So no chances then for the 65816 instructions 'JMP (abs,x)' and 'JSR (abs,x)'? Any hopes for 'BRA' and 'BSR'? 'PSH/PLL zp'? Just kidding. Don't get me wrong, please, I admire your work and I can see the problem. Oh dear, I wish I was able to do a little bit of FPGA programming myself, but I'm too dumb for this. No experience at all. Wouldn't even now how and where to start. My apologies for bugging you.

Anything with the same sequence and cycle count as an existing instruction is likely to be straightforward - so because JMP (abs, x) is the same cycle count as JMP (abs) and because the destination address already passes through the ALU, adding X is probably straightforward.

Done that. How about the additional clock cycle on page boundary crossing (e.g. 'LDA abs, x' and also 'Bcc')? Still the same?

The JMP (abs,X) takes 6 cycles, while JMP (abs) takes 5 cycles. Your idea of adding the X is correct, but you'll have to add an extra state to add in the carry.

... (but it's fine on the 65Org32!)