I bought a C64 in 1984. Soon I was dissatisfied with its performance in BASIC. That's when I purchased a (dis)assembler cartridge.
Later I found out the 6502 is one of the simplest CPUs around. I still like it mainly for its simplicity.

During Basic cold start, it clears the stack by writing $FB into the stack pointer.

In the C64, Commodore calls this a warm start. It restarts BASIC and the shell, but not the kernel (or kernal in Commodore parlance).
The top of the stack me already be in use by the kernel, so it should not be ...

The Commodore 64 uses a 74LS373 octal latch.
You control the latch gate with RAS/ and the 3-state outputs with AEC/

Hi chris,

I checked your PDF schematic and I can't make sense of the reset circuit.
Are you sure you didn't have this in mind?

ROM is not built in, but in de game cartridges only.

Source here

The invalid opcode bytes and their peculiar behaviour are the 'logical don't care' input patterns in combinational logic.

Hi Sergio.

The number of clock cycles documented is the gross cycles requirement. It includes the instruction fetch, execution cycles and all additional bus cycles, until the next instruction's opcode fetch. If one instruction takes x cycles to complete, n consecutive identical instructions take ...

... RDY, /IRQ and /NMI are all tied directly to Vcc instead of going through pullup resistors....
This is completely harmless. It prevents future expansion, that's all.

The 6850's E input not being actively used is more questionable. One might get away with it, but proper operation can't be ...

Having a maximum time to wait for a response is logical -- what if the peripheral never responds?
Handshake acknowledgements can take an indefinite amount of time. The 65C22 was not designed to detect time outs. If your system is in danger of encountering deadlocks, you should have the software ...

Well Ruud, this has been said before: If the datasheet doesn't cover some issue, it is.. err... literally undefined. You can safely assume it is for a reason.

I assume you are using the WDC W65C22S datasheet , as figure and page numbers you mentioned match.
It looks like this datasheet is a mess. The more I looked into the problem, the more inconsistencies, obvious typos and suspicious data I encountered.

The table *does* contain t21 = 535ns max ...

Yes. But come to think of it:
I guess the NMI needs to be edge triggered to prevent unstopable nesting at the blink of an eye.

Unlike IRQ, the NMI doesn't feature a corresponding flag in the status register. I'm trying to figure out the implications.
To me, it seems the 6502 cannot "remember" it is currently running an NMI handler. So the CPU remains susceptible to subsequent NMIs, allowing an indefinite number of NMI ...

Hallo, Ruud

Functional diagram: Omit A or B and the OR gate if it must be susceptible to one edge only.

I'm not a component availability expert, but there are plenty of suitable monostable multivibrators out there.