NMI handler interruptable by another NMI?

raccoon · Post by **raccoon** » Mon Mar 27, 2006 9:50 pm

Unlike IRQ, the NMI doesn't feature a corresponding flag in the status register. I'm trying to figure out the implications.
To me, it seems the 6502 cannot "remember" it is currently running an NMI handler. So the CPU remains susceptible to subsequent NMIs, allowing an indefinite number of NMI levels to nest (assuming there is plenty of time and the stack isn't full).
Does anyone know if my assumption is right, or is there some hidden flag?

Thowllly · Post by **Thowllly** » Mon Mar 27, 2006 10:30 pm

AFAIK, your assumption is right, the 6502 doesn't know that it's handling an NMI so your NMI handler can be interupted by another NMI. But the NMI is edge trigged, not level triggered, so as long as the original NMI source doesn't release the NMI line no new NMIs will be triggered (I dont know the right terminology, I hope you understand what I mean)

raccoon · Post by **raccoon** » Mon Mar 27, 2006 10:50 pm

Thowllly wrote:

But the NMI is edge trigged

Yes. But come to think of it:
I guess the NMI needs to be edge triggered to prevent unstopable nesting at the blink of an eye.

GARTHWILSON · Post by **GARTHWILSON** » Mon Mar 27, 2006 11:22 pm

These things are addressed in the interrupts primer. The NMI portion starts here. Be sure to let it completely load before scrolling, so it will land on the right part of the page.