Hallo allemaal,

I need a circuit that generates a pulse of about 20-30 ns. after every rising or falling edge of PHI2 after 200 ns. Has anybody an idea?
Many thanks in advance.

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That's not very clear. Can you make a timing diagram with ASCII.

Assuming you are using a 1MHZ Clock for your PH2, you could built a 40MHz clock, run it through a counter to divide it down by 40 for PH2. You will have a 25ns pulse 200ns after PH2 hi to low by decoding the 8th pulse. You will have a 25ns pulse 200ns after PH2 lo to hi by decoding the 28th pulse.

Here is an example:


It would take up some hardware, or at least one CPLD, but would be very reliable.

Daryl

Hallo, Ruud

Functional diagram:

Omit A or B and the OR gate if it must be susceptible to one edge only.

I'm not a component availability expert, but there are plenty of suitable monostable multivibrators out there.

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I trust my somewhat flawed English is comprehensible to all.

Use a XOR gate with some kind of delay line. Note that CMOS inverters in the 74AC family have a 4.5ns propegation delay. Therefore, 25ns/4.8ns = just over 5 inverters worth, or precisely what would fit in one chip. Therefore:



That should provide roughly 27ns pulses. If you need wider, use more inverters. Note that the pulses generated will be 4.5ns trailing the respective edge of Phi2.

Could probably make do with just a resistor and the input capacitance
for the delay.

25ns / 5pf = ~5k

(I see 4.5 (typ)-10 (max) pf in the data sheets)

I suspect that the input capacitance of a gate isn't exactly "well defined" any more than the propegation delays are. In fact, I suspect that the *reason* propegation delays are not precisely defined is because of varying input capacitance on gates you connect to it.

I doubt if either way will be particularly accurate. I suspect a chain of
gates will be more consistant.

A single resistor has only one virtue and that's simplicity (if it works
for him)
In general it's probably not a good idea to drive CMOS with slow
changing RC circuits unless there's some hysteresis , but this wouldn't
be that slow. (I think) it'd be roughly like using a passive pull up.
I've never tryed it with 74AC though.

Hallo Raccon,

This is exactly what I already designed, ussing two 74LS221. The reason I asked this question is that I hoped somebody could come with a smaller design. OK, just two IC's and a couple resistors and capacitors is not big but still I had a hope that somebody could even make a smaller design than that.

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Hallo Daryl,

I have thought about that solution too. But I need a replacement for a circuit that is found in http://www.baltissen.org/images/6502c.p ... /6502c.png , three 74LS221 parts found in the middle and bottom of the PNG.
I had hoped for even a smaller design. But your solution needs at least three IC's. Thank you anyway for your input.

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Ack! TTL!

Looks (from the datasheet) like a single 74ls86 quad XOR gate
would do it, two for delay (2 x ~12ns typ) and two for output(s)
(double the fan out, good thing for clocks, at the cost of some
possible skewing)
Being TTL, it's asymetrical but (again from the datasheet)
looks like if you tie the delay inputs together, the HL and LH
delays will be similar.
ie

Heck! Darn! (other obscenities as required)

I miss read the datasheet.

looks like tieing one input low gives the most similar
delays so:



but you still get 10 or 20 ns difference between
the HL and LH edges.
I suppose the difference in delay between tieing the
inputs high and tieing them low could give you a choice
of pulse widths

[quote="bogax][/quote]

Hallo Bogax,

I have seen using a 86 in this way before but didn't think of it. And I'm quite sure I'm going to use it, although in a slightly different way. Many thanks for your input!

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