My name is Sergio and I'm starting a college project to implement (using VHDL) a 6502/6507 processor (or a 6502/6507-like one).I'd like to make this as simmilar as possible to the real processor. I've got some documetation (from this site ) but the information regarding the number of clock cycles used to process each instruction is not clear to me.
My first question is: the number of cycles defined on the documentation is counted from the moment the instruction was already got from memory or it includes the memory access to get it? And how this processing is related to the internally generated clock signals ?
Another question: Is there any documentation with some examples on how the instructions are handled internally on 6052 (micro-codes or a list of which operations are executed in each clock cycle)? It would help me a lot!
The number of clock cycles documented is the gross cycles requirement. It includes the instruction fetch, execution cycles and all additional bus cycles, until the next instruction's opcode fetch. If one instruction takes x cycles to complete, n consecutive identical instructions take exactly n*x cycles.
The number of clock cycles equals the number of bus cycles and an additional one for every internal operation that can't concur with a bus cycle.
Exact details on internal operation are not officialy given. Manufacturers don't publish them AFAIK.
Unfortunately, this opens the door to widespread speculation. Many people believe the 6502 features something they call undocumented instructions. They tend to disagree on the details among themselves.
Good luck with the project!
I trust my somewhat flawed English is comprehensible to all.
The number of clock cycles required to carry out an instruction on the 6502 is something that often mystifies newcomers who have already learned other less-efficient processors like the Z80. The 6502 can do more than one operation per clock, so an instruction takes very few clocks to fetch, decode, and execute. ADC# (add with carry, immediate) is an example given in the programming manual, which says it requires five distinct steps, and yet does it in two clocks, meaning 2us at 1MHz, 200ns @ 10MHz, etc.. That number of 5 could be increased if you add the incrementing of the program counter and the implied automatic CMP#0 instruction; so conceivably you could say it does at least 8 or 9 operations in two clocks' time. This is partly why even in 1980, a Z80 had to go at least 4MHz to keep up with a 1MHz 6502 in terms of how long it took to get a job done.
There are no internally generated clock signals, at least not in the sense of deriving higher internal frequencies or splitting the clock into four phases or anything like that. The 6502 also does not use microcode. The logic is all in hardware. WDC's data sheet tells what is on the bus in individual clocks; but where the processor needs an extra clock here or there before it is ready for the next bus transaction, the data sheet just says "IO" for "internal operation," with no description of what that is.
If you make your own, I would strongly recommend copying the CMOS 6502 (65c02) and not the original NMOS 6502. The difference is not just one of power consumption. The NMOS one had some bugs and various deficiencies and has not been made in about 20 years as far as I know. The CMOS one has more instructions and addressing modes, has all the bugs fixed, is available off the shelf in much higher speeds, and 65c02 cores are being put into products today at a rate of hundreds of millions per year, going into custom ICs in things like camcorders, automobiles, and even life-support equipment.
Last edited by GARTHWILSON on Tue Dec 22, 2009 9:57 am, edited 1 time in total.
Garth, I was under the impression that the inside operations of the 65C02 was a giant databable ROM which would tell the variosu aprts of the 65C02 what to do, similar to the Eagle system mentioned in the book "soul of the new machine". It would be more of a giant state machine. thatr ties in with being able to go most any speed all the way down to DC for operations. I am not sure of how other CPUs i9mplment internal operations.
The 65C02 is, as far as I know, the ONLY CPU approved for medical usage. That version of the chip is way more expensive than the hobbysit grade. It eceeds military spec by a mile. this is because of the extra high quality and record keeping taken to manufature and test out the chips. records are kept even to the location and grade of raw sand for the silicon used in them! This means if you know someone with a computerized pacemaker, the chances are 100% it is 65C02 based.
Racoon: the undocumenteds are simply not implemented inthe earlier 6502 variants, so their actions are somewhat unpredictable. A certain "undocumented" on one manufactor 6502 wont work on another. the 65C02 assigned NOP to all the previously un-assigned opcodes, sot hat takes care of that.
"My biggest dream in life? Building black plywood Habitrails"
Garth, I was under the impression that the inside operations of the 65C02 was a giant databable ROM which would tell the variosu aprts of the 65C02 what to do, similar to the Eagle system mentioned in the book "soul of the new machine". It would be more of a giant state machine. thatr ties in with being able to go most any speed all the way down to DC for operations. I am not sure of how other CPUs i9mplment internal operations.
The picture of the 6502 shows no regular memory-looking area, so I doubt it is employing a ROM. In fact, the overwhelming majority of the die looks like a complete mess (sorry Bill!), which seems to indicate LOTS of independent logic gates. Literally, the single clearest item on the picture of the die is the ALU.
There is of course another approach to be taken -- combination of sequential and combinatorial logic. For example, JSR takes 6 clock cycles, including its opcode fetch. Therefore, it could potentially have 5 flip flops dedicated to it, and the state of those 5 flip flops determines what is going on.
The fact that earlier 6502 variants had such undocumented opcodes that effectively *combined* the effects of two or three instructions lends credence to this design method.
The nuber of clock cycles required to carry out an instruction on the 6502 is something that often mystifies newcomers who have already learned other less-efficient processors like the Z80. The 6502 can do more than one operation per clock, so an instruction takes very few clocks to fetch, decode, and execute. ADC# (add with carry, immediate) is an example given in the programming manual, which says it requires five distinct steps, and yet does it in two clocks, meaning 2us at 1MHz, 200ns @ 10MHz, etc..
...
Well, yes and no.
Your description implies it's superscalar, but it's not. It's pipelined.
Garth, I was under the impression that the inside operations of the 65C02 was a giant databable ROM which would tell the variosu aprts of the 65C02 what to do, similar to the Eagle system mentioned in the book "soul of the new machine". It would be more of a giant state machine. thatr ties in with being able to go most any speed all the way down to DC for operations. I am not sure of how other CPUs i9mplment internal operations.
...
Nope, the 6502/65C02 are not microcoded. Neither are the 6800 or Z80 or other processors of that era, because ROM was too big/expensive.
) but the information regarding the number of clock cycles used to process each instruction is not clear to me.
