You can find some information at

http://www.geocities.com/rmelick/csg.txt

I prefer assembly language, too.

You might found some interesting information about inserting the Realtec 8019 into microcontroller designs at:

http://www.cornelius-consult.de/index.p ... 4&lang=eng

I hope, you will let us know about your progress.

Joachim

I am about 2/3 completed on writing the Ethernet drivers for a Realtek RTL8019AS controller.


That is very interesting to me, because I am working on a similar project, using an old ISA-card with an RTL8019AS. But I am still not got as far as you and just designing the hardware. Have you written ...

Wouldn't you need to also take RDY into consideration as well? For example, if RDY goes low, then the data bus will likely have *data* on it during ph2 low. Or, does the CPU force the data bus with the bank address byte even then?


You are right. That might be a problem. As I normally don't use ...

For my opinion the combination (VPA OR VDA) NAND PHI2 should give the correct timing to latch the upper byte. The part in brackets results in a "valid address" signal, which implies "valid bank address".

Another problem is the need to meet the address hold time after the PHI2 phase. At about 14 ...

Hi Tony,

I am very interested in your computer. Your pictures show the result of many hours of excellent work. I'm looking forward the schematics.

Joachim

As I promised in an earlier post I did some modification to my computer and checked out, if it runs at higher speed. The first modification is the use of fast CMOS devices for the address buffers. Then I changed the direction of the data bus buffer IC2, because the b-outputs have a higher driving ...

I do have a question tho, as I was curious about how you are transfering your rom program to ram for full speed operation - are you using the memory transfer function of the '816, and are you transfering it to the ram that is in frameset0, or another frameset?

Yes, I use one of the block move ...

I'm using the AS-Assembler by Alfred Arnold. It supports many processors (including the 65816) and is freeware. You can find links at:
http://john.ccac.rwth-aachen.de:8000/alf/

The asynchronous bus logic is much simpler than the logic I saw on the PC65816 schematics for clock stretching. It might be of general interest. If anyone wants any details, I'd be happy to provide them. They can go in with the rest of the other mini-HOWTOs on this site.

Because I'm an amateur ...

IMHO the clock generator and the slow down logic will work properly, as long as the slow down signal is asserted early enough, i. e. within phase 1 of clock. The most critical part for higher frequencies is the latch circuit for the addresses 16..23. Since a23 is used for /SLD1, there is just a ...

Hi Garth,

Garthwilson wrote:
Did you determine for sure that the 74HCT541's on the address lines were necessary?


Not really. First I used 74F541 as buffers, but the output signal wasn't very good. So I tried the 74HCT541 and the output signal was much better. As the timing of the address lines a0 ...

Hi Edzard,

after organizing some bulk orders Mike Naberezny now supplies some WDC parts on his website. You should contact him directly.

Joachim

Hi all,

this entry is related to the discussion about a 65C02-based PC under the topic "General Discussions". Unfortunately there are of course many different wishes and opinions and therefore after about one year no practical results. :(

So I have designed a small PC with a WDC 65816, running at ...

Hi River,

try to use the inverted PHI2 bus signal to enable the 245. It may be, that enabling the buffer permanently is responsible for the problem. The 6502 commnunicates just in Phase 2 with external devices.

Joachim