So if I read through the forum, it's clear that the 65816's top 8 address bits (the multiplexed ones) are a nasty quirk.
The version on the datasheet with the latch, inverter, and buffer, gives out at some point. After that, you really need a silicon delay line or other nasty things that has never been described in good enough detail.
Has anybody ever done enough experimentation to give a proper rule of thumb for how fast one can run the 816 before this is a problem? Does the type and speed of the latch, inverter, and buffer make any difference?
Did anybody ever get a proper answer about the top 8 bits?
The faster the clock, the less of a problem the silicon delay lines become -- you require fewer and fewer gates to achieve it.
The answer to this question is elusive because technology is always changing. With a suitably sized PAL chip, or an FPGA, one can decode the bank address byte in real-time, especially if the CPU and the decoder chips are physically adjacent on the motherboard (as they should be anyway).
The answer to this question is elusive because technology is always changing. With a suitably sized PAL chip, or an FPGA, one can decode the bank address byte in real-time, especially if the CPU and the decoder chips are physically adjacent on the motherboard (as they should be anyway).
For my opinion the combination (VPA OR VDA) NAND PHI2 should give the correct timing to latch the upper byte. The part in brackets results in a "valid address" signal, which implies "valid bank address".
Another problem is the need to meet the address hold time after the PHI2 phase. At about 14 MHz I got spikes on the upper address lines, if I used only the end of the PHI2 phase as a criteria for the latching, because the cpu data was still on the bus.
Another problem is the need to meet the address hold time after the PHI2 phase. At about 14 MHz I got spikes on the upper address lines, if I used only the end of the PHI2 phase as a criteria for the latching, because the cpu data was still on the bus.
jdeboy wrote:
For my opinion the combination (VPA OR VDA) NAND PHI2 should give the correct timing to latch the upper byte. The part in brackets results in a "valid address" signal, which implies "valid bank address".
I will need to re-study the timing diagrams, or maybe set up an experiment somehow.
kc5tja wrote:
Wouldn't you need to also take RDY into consideration as well? For example, if RDY goes low, then the data bus will likely have *data* on it during ph2 low. Or, does the CPU force the data bus with the bank address byte even then?