I agree with BDD, I think a CPLD would be a bit easier to work with in this case. Your latches, logic, counters etc can all work within the propagation delay of the single device. With one of the ATF15xx series that can be as low as 7.5ns; so then your limiting factor is making sure your device and ...

I should note that puTTY is not the most intuitive thing to use when it comes to key management. They have their own key store/format for managing keys, which requires extra hoops to get them into the correct format for Github (or just about anything else; a thing I fight with often when I have to ...

That's pretty cool. Might want to add a note to the MOTD that CTRL+C will not stop a program either..... >_>
[Ctrl-C] had no special meaning to traditional UNIX, up to and including SCO OpenServer 7 (the last SCO product which my company sold before going all Linux). To abort a script or program ...

Hey, FYI if anybody wants to have a play around with this system (and admire its primitive nature) I created a website where you can get a live terminal of it in your browser: https://unixv4.dev

Check it out (and let me know if you have any feedback)

That's pretty cool. Might want to add a note ...

I remember my first contact with a computer was a PDP-somethingsomething (PDP-8?) in somewhat 1977/8 during my first year at the "Technische Gymnasium" in the city of Mainz/Germany.

My first contact with a computer was an Apple II+; I never got a chance to work with any minicomputers or ...

Looks like some people have managed to save a real that held the source code for UNIX version 4 and read the data off of it.

The full article can be found on Tom's Hardware:
https://www.tomshardware.com/software/linux/unix-v4-recovered-from-randomly-found-tape-at-university-of-utah-only-known-copy ...

Looks like the new site doesn't load correctly; at least not on Firefox, I haven't tried other browsers.

Thanks, BDD, but IIRC you're providing your PHI1 from the outside, and it is a slightly delayed (ie the propagation delay through a gate) version of PHI2.

IDK, something about using the Pico to generate a clock would be weird; I guess it could be interesting if you're using the Pico as a debugger ...

Now to my question : how do I maintain my latch contents during PHI2 high, and only relatch the bank address at the next falling adge of PHI2 ?
Thanks, in advance !

If I'm understanding you correctly then it sounds like you would want to remove the use of the .LE and .L options and do away with a ...

Okay, after installing Verilator and checking my deisgn, I have worked out what was going on with that BLANK signal. Helps to pick good names for what you're using it for, I was tripping myself up with the name and how I was actually using it..... >_<

That sorted it seems like the other ...

(For that mater I have often just tied the /CE directly to ground for some circuits where I don't really need it.)
My opinion is that is bad design practice. Yes, it will work, but there are potential timing problems with it and most SRAMs (and (E)EPROMs) will draw more current when /CS ( /CE ) is ...

Has anyone experienced or heard of problems when accessing fast memory slowly? Such as 20-55nS sram being accessed with 500nS /CE?

Google and Bing Searches have only given me page after page of Stack -vs- Heap, registers -vs- files -vs- arrays - vs- database queries -vs- etc. Maybe I haven't asked ...

I have not, I'm not sure how this would actually help me.
My timing is correct. Yours isn't.


Near as I can tell my counts are fine, it's my understanding of how Verilog works that was off.

Going over your code in detail shows some rather odd things though, further adding to the confusion ...

Dunno. I tend to avoid the quirky Verilog syntax in favour of the more C style in the example I posted.
"Quirky?" In what way?

And with the latter, I'd expect that to be running at half clock rate. Assuming HC increments with the base clock.
It does update with the base clock (as per the ...

Well making a bit of progress; I've been fiddling with the math some as well as learning a bit more about the nature of Verilog. No good visible progress, but I am getting there I think.... *squints at the monitor*

The big thing I've learned is that despite my best efforts to update the BLANK (or ...