visual6502 Q: Lines crossing at 90°. Connected or not?

[cerebrum]

In the following schematic there are two 90° degrees crossings marked with a red circle:



In both cases are the lines electrically connected or do they just cross over without making contact?

Btw, should I rather post this in the hardware subforum?

[BigEd]

There is a connection in both cases: that's the only intepretation which makes sense. Does Balazs generally use solid dots to indicate a connection, or does he generally use little jumps to indicate no connection? Those two conventions are reasonably standard. It's also possible that it's a mistake not to have drawn connection dots.

Cheers
Ed

[cerebrum]

He uses jumps to indicate no connection. So I will assume no jump implies a connection from now on.

[BigEd]

Do beware that there are few cases where the visual6502 netlist differs from Balazs' schematic: as the visual6502 simulates correctly and the team were working from better photos of a deprocessed chip, we should assume that visual6502 is correct.
It's still an extremely useful (and impressive!) piece of work.
Cheers
Ed

[BigDumbDinosaur]

Most of the electrical drafting programs I've used over the years indicate a connection with a dot at the point of intersection. The jump-over seemed to be more common back when most schematics were hand-drawn. I still use it in my sketches, mostly as force of habit.

[Arlet]

I've also seen the convention where a T-junction always means a connection, and a 4-way intersection means no connection.

[cerebrum]

Let me give a bit more context to the image. The red rectangle marks the area where the smaller pic is taken from. It is from the top left part of the 6502 schematic where the data bus is read in(this corresponds to the bottom right part of the visual6502 simulation because the schematic is rotated 180° in relation to the simulation). The same circuit is repeated for every bit D0-D7:



The complete schematic can be obtained here:
http://www.downloads.reactivemicro.com/ ... onics/CPU/

[cerebrum]

BigEd wrote:

Do beware that there are few cases where the visual6502 netlist differs from Balazs' schematic: as the visual6502 simulates correctly and the team were working from better photos of a deprocessed chip, we should assume that visual6502 is correct.

Yes Ed, I'm using the visual simulator as my primary source and use the schematic only as a guideline/help to understand the simulation.

[GARTHWILSON]

Quote:

Btw, should I rather post this in the hardware subforum?

This one is ok. Since there are so many regarding the visual6502 though (there's nothing wrong with that-- keep it up!), I edited the titles to start with "visual6502:" to make it easier to sort things mentally as one looks down the list of titles.

[BigEd]

Hmm, I'd say these questions are more about the (NMOS) 6502 implementation - visual6502 is just a means to an end. Balazs' schematics and Hanson's block diagram are other sources (as indeed are the original schematics, both Atari's and MOS', for those who have access to them.)

But I'm all in favour of clarity in thread titles.

Cheers
Ed

[cerebrum]

The following is a storage unit from Balasz diagram and the intersecting wires in the red oval do not touch each other(confirmed by visual6502). So the diagram is not totally consistent or maybe it uses the convention that a 4-way intersection means no connection.



Corresponding storage unit in visual6502:

http://www.visual6502.org/JSSim/expert. ... &zoom=12.8

[BigEd]

Mmm, not totally consistent is the best hypothesis.