Vulcan-74 - A 6502 Powered Retro MegaProject

[Oneironaut]

Since I remain as sick as a rabid coyote today, I have the entire day to sit on the couch in front of the wood-stove and solder SRAMs!
Yay... progress.

I now have 5 SRAMs completed, and hope to get at least 10 more today.
At that point, I can start on the new design and just work on the rest of the SRAM when time presents.

Here is what my day is going to look like...


36 pins x 25 SRAMs = 900 Wires!

After chopping all the wires using a jack knife on a cutting board, I then stripped the ends.
I did this by rolling the wire carefully under the blade if the knife, and them pulled off the insulation.
The exposed wire is then soldered slightly at each end, one at a time.

Wires can then be soldered to the pins.
I do this in rows on each side of VCC and ground like so...


Solder to the SRAM, and then bend the wires to the socket.

Now the other side...


Switch sides, and then repeat.

And the final result...


One breadboard ready 10ns 512k SRAM.

Vulcan-74 will require 25 of these SRAMs now...

Code: Select all

2 x 512K : Video Buffer One (492K x 12 Bits)
2 x 512K : Video Buffer Two (492K x 12 Bits)
1 x 512K : Sync Memory (32,768 Bytes)
16 x 512K : Graphics Memory (4MB x 15 Bits)
4 x 512K : Sound Memory (2MB x 8 Bits)

There is also 64K for the 6502 Program Memory, but this will be a different SRAM type.

Ok, I am off to the SRAM factory to burn some solder.

Later,
Radical Brad

[BigEd]

Just tell me this, Oneironaut, do you find yourself dreaming breadboards?

[Oneironaut]

BigEd wrote:

Just tell me this, Oneironaut, do you find yourself dreaming breadboards?

Indeed, some of my most creative (strange) solutions have come from lucid dreams!
There is also this reoccurring nightmare, where I am lost in a giant breadboard city, being chased by an Arduinosaurus-Rex.
Oh wait... that was real.

Brad

[BigDumbDinosaur]

GARTHWILSON wrote:

True, and that's good; unfortunately with any load (like while charging bus capacitance), you get Vcc = Min, IOH = –4.0 mA, IOH(min)=2.4V which will have the effect of slower response by devices that need it pulled up higher. It will take more time to finish bringing the line to a valid CMOS logic-high, since the pull-up current falls way off after the half-way point in the transition. (It won't be a problem the the '816 where you use a 74ACT573 bus transceiver or equivalent anyway though.)

I'm convinced at this point that the '816 has TTL compatible inputs on D0-D7. In both of my POC designs, I am using SRAM with the same voltage output specs as above and they are rock-solid stable.

[Oneironaut]

Sixty percent done the SRAMs now...



Might get a few more done today.
The task wasn't as monumental as I originally thought.

Brad

[GARTHWILSON]

BigDumbDinosaur wrote:

I'm convinced at this point that the '816 has TTL compatible inputs on D0-D7. In both of my POC designs, I am using SRAM with the same voltage output specs as above and they are rock-solid stable.

Your SRAMs' data output does not go directly to your '816 though, right? I think you have a CPLD doing the job of a 74ACT245; so if the SRAMs' output voltage satisfies the CPLD, and the CPLD's output satisfies the 816's data inputs, you're in business.

[Edited to fix where I had said "573" when I meant "245." (The '573 is the bank byte latch, whereas the '245 is the bidirectional data-bus buffer.) Thanks Jeff. I fixed my earlier post too.]

[Dr Jefyll]

Oneironaut wrote:

Brad, I gotta say: you have a real knack with the camera! These puppies look utterly charming -- like cookies that just came out of the oven! So I won't make any suggestions about your baking.

I did have some thoughts about AC performance issues, though. If someday you're gonna do another batch of RAMs -- or if anyone reading this faces a similar wiring challenge -- then you might want to consider the oft-heard advice about keeping capacitor leads as short as possible. The ultimate is to use surface-mount caps instead.

With that other cap of yours removed we see two places where a surface-mount cap could reside.

For mounting right against the IC it's best choose caps that are wider than they are long.

[BigDumbDinosaur]

GARTHWILSON wrote:

BigDumbDinosaur wrote:

I'm convinced at this point that the '816 has TTL compatible inputs on D0-D7. In both of my POC designs, I am using SRAM with the same voltage output specs as above and they are rock-solid stable.

Your SRAMs' data output does not go directly to your '816 though, right?

SRAMs are directly connected to the '816 in both designs. The CPLD in POC V2 strictly acts as glue logic.

[GARTHWILSON]

BigDumbDinosaur wrote:

GARTHWILSON wrote:

BigDumbDinosaur wrote:

I'm convinced at this point that the '816 has TTL compatible inputs on D0-D7. In both of my POC designs, I am using SRAM with the same voltage output specs as above and they are rock-solid stable.

Your SRAMs' data output does not go directly to your '816 though, right?

SRAMs are directly connected to the '816 in both designs.

Then if everything is as it appears, that's more good news about the inaccuracies of WDC data sheets!

[Dr Jefyll]

Inaccurate data sheets aren't the only possible explanation. In regard to a WDC CPU operating with out-of-spec input levels, the question isn't quite as simple as "will it or won't it work?" This is a point you made yourself, Garth, in an earlier post. The chip might work, but with less than the expected speed. I wouldn't have thought of it, but indeed it's thoroughly plausible. Hence it's also plausible that BDD's POC's might be operable at higher than their present speeds were it not for the fact the rated input levels aren't being met. (Apologies, Brad -- we seem to be rehashing the other thread, WDC MPU TTL Compatibility.)

GARTHWILSON wrote:

CMOS gates tend to have a pretty high gain, so there's almost no "no-man's land" around the threshold voltage (which is usually half Vcc). However, there's the problem that the propagation delay through the gate will be much higher if the input goes only a little way into the opposite logic level. IOW, getting the specified speed performance will require getting the input more than just a little way into the logic "1" area. I suspect that's where the 70%-of-Vcc spec comes from. It's not that 52% doesn't qualify as a "1", but that you have to get to 70% for the speed guarantee to be valid.

[BigEd]

Hmm, just because you're out of spec doesn't mean it won't work. And so, if it does work, that doesn't mean you're in spec. Especially when working or not working is such a beast to pin down: works for me, works at room temperature, works with this batch of parts, works with this power supply, works for now, worked last week.

[Oneironaut]

Hey, thanks for the idea. I should have ordered the surface mount caps when I did these.
I shall do that on the next batch of 25 I will need for the hand wired version.

Cheers!
Brad

Dr Jefyll wrote:

Oneironaut wrote:

Brad, I gotta say: you have a real knack with the camera! These puppies look utterly charming -- like cookies that just came out of the oven! So I won't make any suggestions about your baking.

I did have some thoughts about AC performance issues, though. If someday you're gonna do another batch of RAMs -- or if anyone reading this faces a similar wiring challenge -- then you might want to consider the oft-heard advice about keeping capacitor leads as short as possible. The ultimate is to use surface-mount caps instead.

With that other cap of yours removed we see two places where a surface-mount cap could reside.

vt155 rev1.jpg

For mounting right against the IC it's best choose caps that are wider than they are long.

smd cap soldered on J-lead pkg.jpg

[Dr Jefyll]

Glad you like the idea. I admit that, in a breadboard context, keeping capacitor leads that short probably doesn't yield any significant AC performance advantage. But it might reduce crowding, and will probably save assembly time, too.

As you may guess, of the two options I suggested, mounting the cap right against the IC is more finicky. In comparison, it's a slam dunk to plop an SMD between two pins on a .1" grid!

[GARTHWILSON]

Dr Jefyll wrote:

Inaccurate data sheets aren't the only possible explanation. In regard to a WDC CPU operating with out-of-spec input levels, the question isn't quite as simple as "will it or won't it work?" This is a point you made yourself, Garth, in an earlier post. The chip might work, but with less than the expected speed. I wouldn't have thought of it, but indeed it's thoroughly plausible. Hence it's also plausible that BDD's POC's might be operable at higher than their present speeds were it not for the fact the rated input levels aren't being met.

True again, and someone recently posted that they had an '816 running at 16MHz IIRC @ 3.3V, twice the rated speed for that voltage. BDD's POC V.1 runs above the rated speed with that memory and with 45ns ROM. Would it do 28MHz with 5V-output memory (if it weren't held back by the slower ROM? If so, that would be good news too!

[Oneironaut]

Ironically, I just looked in my .1uF cap drawer, and there is a roll of 1000 SMDs sitting right there!
.... next time for sure.

Brad

Dr Jefyll wrote:

Glad you like the idea. I admit that, in a breadboard context, keeping capacitor leads that short probably doesn't yield any significant AC performance advantage. But it might reduce crowding, and will probably save assembly time, too.

As you may guess, of the two options I suggested, mounting the cap right against the IC is more finicky. In comparison, it's a slam dunk to plop an SMD between two pins on a .1" grid!