5719 dissection //partially offtopic

[Dr Jefyll]

Thank you for this, Dieter. A few questions/comments....

ttlworks wrote:

In NMOS, input protection breaks down to having a resistor on diffusion layer
between the pad and a NMOS FET which switches to GND in case of a negative signal voltage,
before said signal enters the first inverter.

Alright, an NMOS input is protected against an incoming signal that tries to go excessively negative (ie, below Gnd). But is there no protection against a signal that tries to go excessively positive (ie, above VCC)? I guess maybe there isn't, but I wonder if I'm missing something. It seems to me that would still be a significant hazard. (And as you say, a CMOS input does have both protections.)

ttlworks wrote:

The designers seemed to have used the "copy&paste" approach for building the logic gates,
means that identifying the logic gates is quite easy.

The layout of a gate sometimes is mirrored, rotated by 180°, or both.
//...But never by 90°.

Never by 90° ??? I wonder, could this be because their CAD tool was simply too primitive? How quaint! (But they still managed to get the job done, which is what matters.)

ttlworks wrote:

A 2:1 multiplexer actually is a quite powerful device:

[...] you creatively wire up the data inputs and the select input of a 2:1 multiplexer,
said multiplexer can replace any type of a two input logic gate.

Allow me to remind everyone that this flexibility is offered for conventional 5V / 3.3V logic as well. See the attached datasheets for the 74LVC1G97 and '1G98. These are handy for late-night logic fixes and also simply to build configurability into your project.

sn74lvc1g97 multifunction gate.pdf

(1.13 MiB) Downloaded 48 times

74lvc1g98.pdf

(1.55 MiB) Downloaded 34 times

ttlworks wrote:

Merry Christmas,
and a Happy New Year.

The same to you, Dieter, and to all our forum members!

-- Jeff

[ttlworks]

Hi Jeff, thanks for dropping by.

Dr Jefyll wrote:

Alright, an NMOS input is protected against an incoming signal that tries to go excessively negative (ie, below Gnd). But is there no protection against a signal that tries to go excessively positive (ie, above VCC)? I guess maybe there isn't, but I wonder if I'm missing something. It seems to me that would still be a significant hazard. (And as you say, a CMOS input does have both protections.)

For NMOS input protection, Frank and me only have seen a NMOS FET
in our previous chip dissections, which was wired up to work as a diode
for clobbering negative voltages to GND.

NMOS input protection conceptually allways had looked more or less
like the PHI2 input pad protection in the 6520:

si6520_1a_phi2.png (10.11 KiB) Viewed 443 times

6520_1a_phi2.png (9.07 KiB) Viewed 443 times

Dr Jefyll wrote:

Never by 90° ??? I wonder, could this be because their CAD tool was simply too primitive? How quaint! (But they still managed to get the job done, which is what matters.)

Never by 90°, and I don't know why.
But it made identifying the logic gates quite fast...
...except that I initially had mistaken the two NOR gates as NAND gates.

One has to zoom in quite close to spot the little difference between
CMOS NAND and CMOS NOR in the metal layer.

Dr Jefyll wrote:

Allow me to remind everyone that this flexibility is offered for conventional 5V / 3.3V logic as well. See the attached datasheet for the 74LVC1G97. These are handy for late-night logic fixes and also simply to build configurability into your project.

Yes, that's right.
But the fun thing about "differential ECL" is that one just has to swap two wires
for integrating an inverter into the input of a logic gate.

For instance, two of the transparent latches in the 5719 are wired in series
to form up a master_slave flipflop which generates the MTROD signal.

The high_active LD of the first latch and the low_active LD# of the second latch are fed by low_active SEL0#.
The low_active LD# of the first latch and the high_active LD of the second latch are fed by high_active SEL0.

This instantly had reminded me to the time when I had tinkered with transistorized
differential ECL flipflops for building a binary counter...

Dr Jefyll wrote:

The same to you, Dieter, and to all our forum members!

Thanks, Jeff.

[BigEd]

All very good work, well done!

If you have to guess which are NMOS and which PMOS transistors, you'll usually find the PMOS are larger/stronger with a wider channel (which is to say, longer poly gate).

[fhw72]

BigEd wrote:

All very good work, well done!

If you have to guess which are NMOS and which PMOS transistors, you'll usually find the PMOS are larger/stronger with a wider channel (which is to say, longer poly gate).

Yes. These are the two criteria I use to distinguish them:

1. Size/Width
2. Connection to GND or VCC.

Some time ago I also started vectorizing an old CMOS Chip which uses a process without polysilicon: Metal-Gate... very cumbersome.
I still haven't finished it.