Thank you for this, Dieter. A few questions/comments....

Alright, an NMOS input is protected against an incoming signal that tries to go excessively negative (ie, below Gnd). But is there no protection against a signal that tries to go excessively positive (ie, above VCC)? I guess maybe there isn't, but I wonder if I'm missing something. It seems to me that would still be a significant hazard. (And as you say, a CMOS input does have both protections.)

Never by 90° ??? I wonder, could this be because their CAD tool was simply too primitive? How quaint! (But they still managed to get the job done, which is what matters.)

Allow me to remind everyone that this flexibility is offered for conventional 5V / 3.3V logic as well. See the attached datasheets for the 74LVC1G97 and '1G98. These are handy for late-night logic fixes and also simply to build configurability into your project.



The same to you, Dieter, and to all our forum members!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hi Jeff, thanks for dropping by.


For NMOS input protection, Frank and me only have seen a NMOS FET
in our previous chip dissections, which was wired up to work as a diode
for clobbering negative voltages to GND.

NMOS input protection conceptually allways had looked more or less
like the PHI2 input pad protection in the 6520:





Never by 90°, and I don't know why.
But it made identifying the logic gates quite fast...
...except that I initially had mistaken the two NOR gates as NAND gates.

One has to zoom in quite close to spot the little difference between
CMOS NAND and CMOS NOR in the metal layer.


Yes, that's right.
But the fun thing about "differential ECL" is that one just has to swap two wires
for integrating an inverter into the input of a logic gate.

For instance, two of the transparent latches in the 5719 are wired in series
to form up a master_slave flipflop which generates the MTROD signal.

The high_active LD of the first latch and the low_active LD# of the second latch are fed by low_active SEL0#.
The low_active LD# of the first latch and the high_active LD of the second latch are fed by high_active SEL0.

This instantly had reminded me to the time when I had tinkered with transistorized
differential ECL flipflops for building a binary counter...


Thanks, Jeff.

All very good work, well done!

If you have to guess which are NMOS and which PMOS transistors, you'll usually find the PMOS are larger/stronger with a wider channel (which is to say, longer poly gate).

Yes. These are the two criteria I use to distinguish them:

1. Size/Width
2. Connection to GND or VCC.

Some time ago I also started vectorizing an old CMOS Chip which uses a process without polysilicon: Metal-Gate... very cumbersome.
I still haven't finished it.