Look ma', no bodges!

The boards came in and I just soldered everything. It took about 1.5 - 2.0 hours to solder everything and tidy it up. And most importantly, no bodges.

I did learn a few things here though:

1) The purple board is unusually dark for me, and I don't have a lot of good lighting in the office anyways. I was basically soldering blind. My daughter chose purple because it's technically her computer I prefer the classic green.

2) Some of the silkscreen from the gerbers didn't show up on the board! None of the 5 boards from JLCPCB had one particular silkscreen label. I checked the gerbers and they have it, so... IDK there.

3) In the future I need to look more closely at physical dimensions of components on Mouser. My expansion port 1x20 pin headers are super tall, and my 0.1uF bypass caps were not my favorite with the bent leads for easy insertion.

The next thing to do is try to attach the 6522 VIA through the expansion port. That will be a fun exercise!

More updates to come when they come. Thanks everyone!

Chad

Looking good Chad! Are you starting to think about case / mounting options?

_________________
"The key is not to let the hardware sense any fear." - Radical Brad

Thanks! This board has a Mini-ITX form factor, so it can actually fit in any ol' desktop PC case, or smaller ones too. That's why it's such a huge board with so much wasted space near the bottom. I personally would like to just use 2 pieces of plexiglass eventually.

Chad

Alright! Now the 6522 VIA is working also! Attached are pictures.

I have made *one* tiny little bodge now, adding PHI2 to my expansion port. Like, why *didn't* I design it like that. Duh.

I have also updated my Github with the adjusted schematics and gerbers.

Still more testing to do. I would like to see if I can get the PS/2 Keyboard exclusively off of the VIA. And of course an LCD is in the future. Lastly, I'd like to hook up the Genesis controller and somehow play Tetris and Space Invaders with that!

Thanks everyone. Today was a good day.

Chad

Hi Chad, great that the new board is working!

I had a couple of questions about the PCB design:

1. What settings do you use for trace widths and clearances?

2. Did you figure out why some of the graphics were missing? Was it on the wrong layer, or maybe lines that were too thin to print?

Hi George! Glad to hear from you!

1) Um... good question. I would have to look at my computer at the house again. Almost all signal traces and vias are the default KiCad values, which I *hear* are pretty large. The power/ground traces and via's are a bit larger. I will see about getting those specifics to you later.

2) Are you talking about page 1 stuff? So CLK is my 25.175 MHz clock and /CLK is inverted. I had been using /CLK for latching and shifting the sync signals and color data. I needed to use CLK instead. Essentially it latches that sync and color data when PHI2 rises, when before I was trying to do it too early. Ever since I used the CLK signal instead it has been super solid and no issues at all. I see a tiny tiny amount of jail bars when the page is full-white, but the monitor and even televisions have been happy with it.

Thanks!

Chad

I meant regarding this point, I'm interested in why they left it out.

Oh! I have no clue. I see the silkscreen on the gerbers. No indication as to why it would be missing. Oh well, I'll double check on JLCPCB gerber view later.

For the sizes of the traces:

Power and Ground: Track 0.02000 in, Vias 0.03500 in / 0.01500 in
Signals: Track 0.25 mm, Vias 0.8mm / 0.4 mm (KiCad defaults)

Chad

Great, thanks. So far I've been quite cautious, using a coarse grid (0.05 in I think) so lots of space between traces, but I recently looked up the fab's capabilities and reduced this down (grid size of 0.025in, trace width 0.25mm for signals 0.42mm for power/gnd, minimum clearance of 0.2mm but generally more like 0.3mm or 0.4mm due to the grid size). You have a few cases there with a lot of traces routed very close to each other, closer than I am doing I think, so I'm glad to hear it works well as it gives me hope for my design, which is quite densely-packed and very congested!

Last PCB I had made was 0.1mm trace, 0.1mm clearance, vias 0.4mm outer, 0.2mm inner. 4 layer boards allow finer traces than 2 layer (0.09mm versus 0.127mm at JLCPCB). There didn't seem to be any problems with the board, although I notice they have increased their minimum via size to 0.45mm now.

I'm a little more conservative: I generally use 6 thou/0.15mm for signal traces with 0.6mm/0.3mm vias. Again, JLCPCB.

I found a European PCB house that offered sane prices for prototype board but their smallest vias were 0.7mm/0.3 which broke my PCBs. (And I can't recall which one it was, so I can't check if it's changed!)

Neil

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I have a question, but let me lead up to it first.

So I have the VIA attached to the board, and it uses a lot of signals directly from the 6502. Everything is working fine, but when I probe the R/W line everything crashes. If I unattach the VIA and probe that line, it's fine.

Initially I had a 10K pull-up on the R/W line, because I'm using BE and it floats for a tiny bit and figured it wouldn't hurt to have it on there. I just changed it to a 3.3K pull-up and it no longer crashes when I probe the R/W line anymore, even with the VIA attached.

I mean, sure, it could be a timing issue. But it seems to happen when I probe the /RESET line also, which is weird and definitely not a timing issue. I tap the probe on the /RESET line and it either crashes or resets the system. Hm. I have a MCP130 with 5K internal pull-up plus a 10K external pull-up on the /RESET line, btw.

Attached are schematics.

My question(s): Why would probing a line make the system crash? Obviously the probe itself is changing the signal, but in what way? I cannot unprobe it and *see* what it looks like, then probe it and see what it looks like, so I cannot compare/contrast between the two states. I remember there was a video Garth had mentioned, something like, "I just probed it and it crashed!" or some such, would that have the answer? Is this behavior due to AC performance (what *does* AC stand for anyways?) because I have the VIA tethered to the 6502 on a separate breadboard?

I added that 10K pull-up to R/W just because, figuring it was not necessary, but it seems I needed something even more than that!

Thanks for any insight.

Chad

Your probes should be set to 10x, and the scope adjusted accordingly, so that probing puts less load on the signal being probed.
viewtopic.php?p=89780#p89780

But perhaps you should share a photo - maybe you are probing in some unexpected way. You should, for example, be picking a reference ground that's close the signal you're probing. And, naturally, you need to be very careful not to disturb or short anything while probing. (Perhaps you yourself should also have an antistatic wrist strap and a good ground. Especially if you're the kind of person who gets static shocks.)

Here's the video: https://www.youtube.com/watch?v=MJpDFnRQw8s

It's worth watching a few times; it's only 12 minutes long!

AC is "alternating current."

_________________
"The key is not to let the hardware sense any fear." - Radical Brad