Strange memory write problems

[BigEd]

Excellent! I did have a thought: perhaps you could see if a lower supply voltage would help - perhaps by putting a diode inline. But that wouldn't tell you a great deal, without some instrumentation.

[plasmo]

My background is in hardware so I read this thread with good bit of interests but since you already have several experts on the case, I didn't think I can add much value. However, at this point I feel the root problem is being covered up with pull up resistors and ground/VCC modification. Adding ground/VCC to make the problem show up frequently is a good thing. The worst problem to solve is an intermittent problem so anything you can do to make it happen frequently is a good thing. I think signal contention is a strong possibility where better ground/vcc can shift the point of contention to make the problem better or worse. Lower supply voltage will also shift the point of contention. You should probe every signal with a scope and should never see lingering mid value of 1.4 to 2V; signals should transition rapidly from ground to logic high (3V and above).

Your design is solid; you should not see these problems. The problem is likely a mechanical issue (short, open) somewhere in the board. If no signal contentions are observed and intermittent problem persisted, building second board or have another person build a board in parallel may be the best solution forward.
Bill

[Dr Jefyll]

Good point, Bill, re a possible mechanical issue (short, open) somewhere in the board.

Adrian, one way you can explore that is by applying some vibration. Nothing too violent, mind you. Just use your own judgment re how much is safe. My own approach is to grasp a screwdriver by the wrong end and use it as a little hammer, striking the DUT with the screwdriver handle. If a failure coincides with one of the blows then that's a pretty significant clue...

-- Jeff

[BillO]

plasmo wrote:

However, at this point I feel the root problem is being covered up with pull up resistors and ground/VCC modification.

My thoughts exactly.

Just a question for Adrian though .. Are the 6551 ACIAs older NMOS style or CMOS?

Edit: Never mind. I can see in the picture.

[adrianhudson]

Hello Everyone and thanks for your replies and greatly appreciated thoughts.

I have been messing a little.

I have a number of ROMs with known working programs (on the breadboard that was used as the prototype for this board). They partially work but usually just stop responding after a few instructions. I even had one program that was responding to interrupts even though I had quite plainly turned them off with SEI. Now, that's just weird.
A little while ago I swapped the 65C02 for another one and a program that wouldn't run properly before ran perfectly - it was a clock program with interrupts updating the time in the background and a foreground task displaying on the LCD. It even had a routine to get the time using I2C at startup that worked. I powered it down and up again and I can no plonger get it working.

This is pointing to some mechanical problem that I can't find - exactly as you seem to be gravitating to. I don't think it was the fact I changed CPU chip, just the fact I had poked about. I am still waiting for the Rockwell 65C02 to arrive and I am going to give that one last try before starting a rebuild. I have spent the last month of (most) eveings debugging this thing. My other half is being very patient I could rebuild it in a few eveings and probably imporve the layout while I am at it.

May I ask for some advice. Should I either use the Rockwell CPU without pull-up resistors in the new build or the WDC 65C02 with resistors?

My list of parts in my parts box are:

WDC 65C02
Rockwell 65C02 (soon!)
2 x Rockwell 65C51 P2
1 x WDC W65C51N
2 x WDC W65C22S
My RAM is Alliance AS6C62256

I could do:
WDC CPU; WDC 65C22S x 2; WDC 65C51N x 1; Rockwell R65C51 + pullup resistors
or
WDC CPU; WDC 65C22S x 2; Rockwell R65C51 x 2 + pullup resistors
or
Rockwell CPU; WDC 65C22S x 2; Rockwell R65C51 x 2 with no pullup resistors (or would I need them for the WDC 65C22S chips? Or should I source some Rockwell 65C22s?

Any other advice?
Thanks folks!

[BillO]

You don't need pull-up resistors at all. You have a full CMOS environment. Those memory chips will perform just fine given the maybe 40-50 uA loading you have.

The Rockwell 65C51 chips have the benefit of not having a transmit bug to code around.

[Dr Jefyll]

adrianhudson wrote:

Should I either use [...]

Use sockets! And, at least consider including a socket for a SIP resistor array (yes, pullups). Your Rockwell 'C02 surely won't benefit from them but your WDC just might. Or not, but a socket for a 9-pin SIP is inexpensive and small.

BillO wrote:

You don't need pull-up resistors at all.

I tend to agree, but at the very least I think we can agree there is a degree of compromise involved, albeit perhaps debatably significant.

BillO wrote:

You have a full CMOS environment.

Check out the datasheet for this CMOS ram.

Quote:

The CY7C109D/CY7C1009D device is suitable for interfacing
with processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.

sram 5V 128Kx8 CY7C109D_CY7C1009D_1-Mbit_(128_K_8)_Static_RAM-DataSheet-v11_00-EN.pdf

(876.93 KiB) Downloaded 115 times

-- Jeff

[adrianhudson]

Dr Jefyll wrote:

... And, at least consider including a socket for a SIP resistor array (yes, pullups).

What a good idea.

[BillO]

Dr Jefyll wrote:

adrianhudson wrote:

Check out the datasheet for this CMOS ram.

Your point is taken Jeff. Two things though..

1) my comments were based on teh chips he is using.
2) That Cypress chip is a fairly atypical chip and seems to have some unusual architecture to enhance speed, reduce supply voltages and reduce die size. I would be willing to bet that the 5V parts are internally regulated down to a lower voltage to allow them to use 3.3V chips. That way they don't have to create a specific 5V part. Probably a good idea to stay away from Cypress 90nm memory technology for our purposes.

[GARTHWILSON]

The data sheet for the Aliance AS6C62256 he says he's using (or at least has in his parts box) also says only 2.4V minimum VOH with only 1mA load.

[BillO]

It looks like he only has about 1/20 of that.

[GARTHWILSON]

1/20 of the current? It takes a time to charge up the parasitic capacitance. To go from, say, 1V to 3.5V (a 2.5V swing), if the current is 1mA average (much higher to start, but tapering off to near zero as it gets above 3V), charging up 30pF of capacitance would take 75ns, mostly added to the access time. The access time is specified for a 50pF load, but only to the time it reaches 2.4V which will be long before it reaches a valid CMOS logic '1' when the current has dropped off so severely at the VOH. So depending on the glue-logic speed, even at 1MHz I wouldn't rule out a chance that pull-up resistors could take care of it.

[BillO]

Why would the current drop off like that above 3V? The spec sheet says a minimum of 1mA @ 2.4V which implies an internal resistance of 2.6K. If that stays constant then current would be .77mA @ Vo=3V and .38mA @ Vo=4V. That's if the internal resistance stays constant. The behavior of small MOSFETS is that their drain resistance decreases as the current through them also decreases.

The WDC stuff only requires Vih > 3.5V, the RAM and ROM are okay with TTL levels.

[floobydust]

Well, having reviewed the schematic multiple times, I don't see anything that stands out as a problem. It should work... the fact that it doesn't pretty much gets down to either a bad chip, bad socket, possibly some other bad parts or a problem with construction.

If I were to start a build again, I'd go with the WDC 65C02 and 65C22, use the Rockwell R65C51 ACIA, the Alliance RAM and the 74HC logic chips. As for ROM/EEPROM, just stick with a common Atmel AT28C256. Beyond that, multiple 0.1uF bypass caps and a couple decent size electrolytic caps and you shouldn't have a problem.

As for construction, build up the board and run a solid ground between all of the chips first, then add the 0.1 bypass caps to each chip, then connect a +5V power line to each chip. I'd also suggest taking a picture of this and posting it before going any further. Most of my early wire-wrap projects used some proto boards that had bus patterns which could be used for power distribution. I used them to to distribute the ground and +5V to each chip and ensured that I had a solid ground and voltage feed to every component that needed them before moving to the next stage of construction.

On an odd note... are you absolutely certain that your EEPROM/ROM chip is properly programmed and can pass a verify from the programmer? Also make sure you have a solid 5V power supply with ample current, good regulation and low noise. Also make sure you have a solid connection for the power supply that doesn't glitch if you move a wire around.

Good luck...

[GARTHWILSON]

BillO, the internal resistance won't stay constant. Even WDC's W65C22S will do 19mA pulling up to 4.2V, which with my 5.08V power supply, means 46Ω; but if you short it to ground and try to pull it up, you'll only get 50mA, which means 100Ω. IOW, it's not linear. I did an experiment on a 74LS04 in July, and with a 4.97V power supply (as close as I could get it to 5V with the single-turn pot on the power supply), I got this:

Code: Select all

No load:  VOL=.16V, VOH=4.41V!
Pulling up against different pull-down resistors:
pull-                      internal
down    V(out)   I(out)    resistance to Vcc
12K     3.54V    295µA     4.85K
6.8K    3.51V    516µA     2.83K
3.9K    3.47V    890µA     1.68K
2.2K    3.44V    1.564mA   978Ω
1.5K    3.40V    2.27mA    692Ω
820Ω    3.33V    4.06mA    404Ω
470Ω    3.23V    6.87mA    253Ω
100Ω    2.20V    22mA      126Ω

If we re-calculate the internal resistance to a constant internal voltage drop below Vcc of 4.97V-4.41V=.56V (which I know is a bit of a simplification of the voltage drop across a silicon P-N junction since it will increase a little bit with current), we get:

Code: Select all

pull-                      internal
down    V(out)   I(out)    resistance to 4.41V
12K     3.54V    295µA     2.95K
6.8K    3.51V    516µA     1.74K
3.9K    3.47V    890µA     1.06K
2.2K    3.44V    1.564mA   620Ω
1.5K    3.40V    2.27mA    445Ω
820Ω    3.33V    4.06mA    266Ω
470Ω    3.23V    6.87mA    172Ω
100Ω    2.20V    22mA      100Ω

I was glad to see it did so much better than specified; but still, output got awfully weak before reaching 3.5V, and clearly it does not behave like a resistor. What's in his SRAM is anybody's guess, until someone does a similar experiment; but the fact that it cannot pull up hard insinuates that it's something similar, unlike a CMOS output which can pull light loads all the way to the positive supply rail.

One device with TTL-type outputs may be specified to be faster than another device with CMOS outputs, and yet for driving CMOS inputs and the capacitance on the line, the supposedly slower CMOS output may get the CMOS input to recognize a valid '1' sooner than the TTL one does, something like this:

TTL-CMOSthresholdTime.gif (14.94 KiB) Viewed 1435 times