PHI1O on a W65C02

[sburrow]

Hello everyone,

I'm looking over my hardware designs for my next board, and I am one inverting gate short. No fear, the 6502 has an inverted PHI2 line called PHI1 already built in! I'm focusing exclusively on the W65C02 here, and will call it PHI1O for forum-search purposes.

I know the datasheet says it's untested. I know the datasheet does not recommend using it. But I don't want to add another chip to the board, and it seems to be working fine. Attached below are some pics I took from my scope just now on my current board. Sorry for the dirty signal, "not all ground is ground" and I was too lazy to do a perfect job (plus my scope isn't super great either).

The top is PHI2 (not PHI2O!) and the bottom is PHI1O. The delay between them is... near instantaneous. I think I see at most 10 ns delay when zooming in. I would get something similar from a 74HC04 anyways (here https://assets.nexperia.com/documents/d ... _HCT04.pdf).

Why did I think this was ok at all? On Garth's site, on the potpourri page (here http://www.wilsonminesco.com/6502primer/potpourri.html), he says:

Quote:

WDC no longer tests or specifies the gate delays between Φ0 in, Φ1 out, and Φ2 out for their newer 65c02's, and they would prefer that the designer use the external oscillator option. All the same internal inverters seem to still be in place however, so I have little doubt that the circuit above will still work fine; but I had to pass the info on. If you do it per WDC's preference, the output of your external oscillator (probably an oscillator can) goes to everything requiring Φ2, and pins 3 and 39 go unused.

I'm not using PHI1O for external oscillator purposes, just for logic, but the principle still holds: PHI1O should work. I have confirmed this on my own scope.

Any grievances? Suggestions/warnings?

Thank you everyone.

Chad

[floobydust]

First, you can't argue with success.. as it is working. Then again, WDC has their status regarding those signals and that their datasheet lists all timings not using those signals. There's also no guaranty that those signals will work in future produced chips.

Realistically, I don't see that changing, as there's no actual reason for WDC to change the chip for any reason. Unless you're planning to go into production, I doubt you have anything to worry about... and even then, unlikely.

As a picture is worth a thousand words, getting the bigger picture (on your new system) might yield some different views on how to accomplish what you need. Also, if you feel the need to add the extra inverter, note that with SMT devices, you can get a single inverter package these days, and not have 5 leftover inverters in the 'HC04 package.

https://www.mouser.com/datasheet/2/916/ ... 529799.pdf

[AndersNielsen]

It’s less of a problem using it on the C02 than the NMOS - but it’s hard to say how much you can load it before you run into issues. More than the NMOS - less than a HC inverter.
You’ll probably be fine - I was for a few designs but you’ll probably be better off in the future if you leave those two pins alone

[sburrow]

floobydust wrote:

Realistically, I don't see that changing, as there's no actual reason for WDC to change the chip for any reason. Unless you're planning to go into production, I doubt you have anything to worry about... and even then, unlikely.

Thank you. I'm personally against using SMT parts right now. Not that I can't solder it, I'm sure I could, just now is not the time.

You mention 'production', which is always my mindset. I purposely choose designs using chips that are currently (and futuristically) commonly available. What *if* I want to make a 1000 of them for whatever reason? Better to not use new-old stock.

AndersNielsen wrote:

but it’s hard to say how much you can load it before you run into issues

Hm! Now THAT is a good point. I hadn't thought of the load. Thank you.

So, let's say I want to use a transistor to invert the signal:

https://electronics.stackexchange.com/q ... tal-signal

Just how fast can these go? I'm running this 6502 at 3.14 MHz, and I'm already planning on using transistors in my video circuit running at 25.175 MHz. Still, have any of you used a transistor as a (reliable) inverter before?

I could of course use a transistor on some piece of logic that is not as critical or slower as PHI1, and use my 74HC04 for PHI1. I've been thinking about it for a while. Still, this seemed like a free inverter, and... well, it looks like it works.

floobydust wrote:

As a picture is worth a thousand words, getting the bigger picture (on your new system) might yield some different views on how to accomplish what you need.

I'm not quite ready for that yet

Thank you both, good points.

Chad

[GARTHWILSON]

Don't use the transistor for this application. Suppose you had a 1.5K resistor for the pull-up, and a load that was 30pF including all inputs, sockets, board traces, etc.. The rise time to a valid logic '1' would be 1.5Kx30pF=45ns. With a 3.3K resistor and 30pF, it would be 99ns. That's actually the time constant, ie, the time needed to rise to 1-1/e times the full voltage excursion. Rise time in CMOS circuits however is usually measured from the 10% to the 90% points of the power-supply voltage, which would be even longer. Further, these numbers assume you put a 33pF or 47pF capacitor across the base resistor so you don't add yet another RxC delay charging up the base capacitance, and it assumes that the transistor is infinitely fast, or at least fast enough to not add significantly to the other delays. As you can see, it's not a good way to do it.

[BigDumbDinosaur]

If you’re that worried about performance, use 74AC or 74AHC logic, not 74HC. Better yet, for a single inverter, there is the 74LVC1G04, which has a guaranteed tPD of 3.3ns or better. Plus it has 24ma of drive in both directions, equal to the output of a 74AC gate.

Per WDC’s recommendation, I would not use the 65C02’s clock outputs in a new design. Their performance is unpredictable, and variances in internal gate delays could create hard-to-debug timing issues for you.

[sburrow]

BigDumbDinosaur wrote:

Per WDC’s recommendation, I would not use the 65C02’s clock outputs in a new design. Their performance is unpredictable, and variances in internal gate delays could create hard-to-debug timing issues for you.

Alright, y'all sold me

GARTHWILSON wrote:

As you can see, it's not a good way to do it.

So why is it ok for me to use them for 0V to 1V? [ As per previous topic... somewhere. ] Is it all about timing? So it takes a long time to go from 0V to 5V, but it doesn't take as long to go from 0V to 1V? This whole thing scares me all over again on yet another thing where I "figured it was good to go" but perhaps it wasn't. I will be going with a method I have already been using on previous boards instead of radical changes and hoping for the best.

Good points for sure, thank you all very much.

Chad

[BillO]

sburrow wrote:

So why is it ok for me to use them for 0V to 1V? [ As per previous topic... somewhere. ] Is it all about timing?

Chad

I believe the other circuit was just a video data stream so precise timing would not be an issue. Here it might be.

It depends on what you are driving with this signal as to what kind of PD you can tolerate and what kind of load you have. A small MOSFET or transistor might work just fine in you have a single CMOS load with little parasitic capacitance and use a 300 ohm pullup and the resulting PD is tolerable. I don't think we have enough information to give you a reasonable response.

You could include a kludge/proto-typing area on your new board and make the extra 5 inverters available to that area for future consideration and just go ahead with the 74HC04. Just a thought.