W6502SBC, a simple 6502 sbc

[willie68]

An old topic has been bothering me for a long time. Assembler and 6502. My C64 has been mothballed for a long time, the VC20 is selling. Nevertheless, I find the 6502 very interesting in terms of assembly language. What you could do with 1MHz and 64kb RAM. This year (2022) the time had come. I decided to build a 6502 SBC. There are many, many posts and suggestions here and on the Internet about this. Unfortunately, there is no version that you could easily rebuild and that meets my expectations of a 6502 workbench computer. Here are my requirements in brief:

- WDC65C02 CPU with 4MHz
- WDC65C22 VIA with 4MHz
- 6551 ASIC for the serial port (R65C51)
- 32Kb or 64KB SRAM (both were available)
- EEPROM or Flash as Kernal/Basic ROM
- NMI and IRQ assignable
- Variable memory allocation, possibly also modifiable from the outside
- Plug-in card system or system bus, preferably with corner edge connectors, as in the C64, VC20, a suitable backplane would be nice
- no video, audio or anything
- SPI over 6522, so you can connect a display/keyboard
- CPLD for something
- opt. LC display

Follow the steps to learn:
- CLPD
- build a simple system on breadboard with 1MHz or with a simple pcb

At the end of the first section there should be a CPU card with a working 6502 system. Incl. BASIC via terminal. VTL-2 and Basl (my own small language) would be considered as further languages. And of course a version of the TPS.

More information and project logs are here:
https://github.com/willie68/w6502sbc

For the latest progress check out my Hackaday page. However, the build log is in German.
https://hackaday.io/project/186414/logs

But I'll try to keep you posted here as well. (in english, of course)

[willie68]

to describe the current status,
here is the circuit diagram,

schematic V1

a 3d version of the board.

pcb 3d

And here I have the current status of address decoding,

Code: Select all

header:
Name     adr_simple ;
PartNo   01 ;
Date     24.07.2022 ;
Revision 03 ;
Designer wkla ;
Company  nn ;
Assembly None ;
Location  ;
Device   G16V8 ;

pld:
/* *************** INPUT PINS *********************/
PIN [1..8]   =  [A15..A8]; 
PIN 9   =  PHI2;

/* *************** OUTPUT PINS *********************/
PIN 12   =  CSRAM;
PIN 13   =  CSHIROM;
PIN 14   =  CSEXTROM;
PIN 15   =  CSIO;
PIN 16   =  CSIO3;
PIN 17   =  CSIO2;
PIN 18   =  CSIO1;
PIN 19   =  CSIO0;
/* *************** LOGIC *********************/

FIELD Addr = [A15..A8];
CSRAM_EQU = Addr:[0000..7FFF]; // 32KB
IOPORT_EQU = Addr:[B000..BFFF]; // 4KB
VIAPORT_EQU = Addr:[B000..B0FF];
ACIAPORT_EQU = Addr:[B100..B1FF];
CSIO2PORT_EQU = Addr:[B200..B2FF];
CSIO3PORT_EQU = Addr:[B300..B3FF];
CSEXTROM_EQU = Addr:[8000..AFFF]; // 12KB
CSROM_EQU = Addr:[C000..FFFF];  // 16KB

/* ZP */
CSEXTROM = !CSEXTROM_EQU;

/* RAM */
CSRAM = !CSRAM_EQU # !PHI2;

/* 8kb of ROM */
CSHIROM = !CSROM_EQU;

/* IO */
CSIO= !IOPORT_EQU;
CSIO0 = !VIAPORT_EQU;
CSIO1 = !ACIAPORT_EQU;
CSIO2 = !CSIO2PORT_EQU;
CSIO3 = !CSIO3PORT_EQU;

simulator:
ORDER: A15, A14, A13, A12, A11, A10, A9, A8, PHI2, CSEXTROM, CSRAM, CSHIROM, CSIO, CSIO0, CSIO1, CSIO2, CSIO3; 

VECTORS:
/* internal RAM */
0 X X X X X X X 0 H H H H H H H H 
0 X X X X X X X 1 H L H H H H H H 

/* 8000-AFFF external Rom */ 
1 0 0 0 X X X X X L H H H H H H H 
1 0 0 1 X X X X X L H H H H H H H 
1 0 1 0 X X X X X L H H H H H H H 

/* IO */ 
/* CSIO0 */
1 0 1 1 0 0 0 0 X H H H L L H H H 
/* CSIO1 */
1 0 1 1 0 0 0 1 X H H H L H L H H 
/* CSIO2 */
1 0 1 1 0 0 1 0 X H H H L H H L H 
/* CSIO3 */
1 0 1 1 0 0 1 1 X H H H L H H H L 
/* nicht direkt benutzt */
1 0 1 1 0 1 X X X H H H L H H H H 
1 0 1 1 1 X X X X H H H L H H H H 
/* ROM */
1 1 X X X X X X X H H L H H H H H 

[akohlbecker]

Welcome! Thanks for sharing your project. Eager to see the final result!

[floobydust]

First, Welcome and thanks for posting info on your SBC plans. Not sure where you are in Germany, but I used to travel there extensively during the 90's and 2000's... and lived for a couple years in Reutlingen.

So, I've looked at your schematic and browsed your PLD code... here's come comments in no particular order:

- Power supply: as you're using an input diode for blocking reverse voltage, why not replace it with a full-wave bridge? This would allow any polarity on the input and always power the SBC.
- 16V8 PLD: I would recommend using the 22V10 instead. It has more lines and would be a better glue chip. I used one in my C02 Pocket SBC and my Github page has the schematic and code for it.
- R65C51: This is a very old design, really for modems. Note that the older Rockwell parts are not easily found, much less in the higher 4MHz versions. Also note that the recent WDC W65C02 part has a defect with the transmit bit in the status register - there's a long post on the forum here that covers that in gory detail. Using a newer UART/DUART would be a better choice. I (and several others) have switched to NXP chips, mostly the SC28L92 DUART which has two serial ports and a counter/timer.

Also, when coding the PLD, it's best to keep the chip select lines decoded only using the address lines from the CPU. You do need to qualify the Write (and Read) signals for memory and other device to Ph2 clock. Using the 22V10, you can have qualified Read and Write signals, RAM and ROM select lines and 5- I/O selects that are 32-bytes wide.

Note: If you switch to a NXP DUART, you will need an inverted Reset line for that chip. I used a TL7705 which generates both Reset and /Reset and use a DS1813 as an NMI trigger with a momentary switch to trigger a Panic routine.

If you use a larger RAM chip, you can easily change your memory map (just recode the PLD) to get more contiguous RAM memory if needed. Also, where you decode your I/O can make a difference in how you can manage your memory mapping. I always use Page $FE for hardware I/O. This allows a more flexible memory map for contiguous memory.

FInally, best of luck on getting your SBC up and running... there's lots of expertise out here... just ask if you have any questions... and have FUN!

[BigEd]

(Great! And thanks for linking your sources and logs.)

[willie68]

floobydust wrote:

First, Welcome and thanks for posting info on your SBC plans. Not sure where you are in Germany, but I used to travel there extensively during the 90's and 2000's... and lived for a couple years in Reutlingen.

Thanks for the welcome. I live in Hattingen, near Bochum, Ruhrgebiet.

floobydust wrote:

- Power supply: as you're using an input diode for blocking reverse voltage, why not replace it with a full-wave bridge? This would allow any polarity on the input and always power the SBC.

It's only a insurance against reverse polarity. I have always an 9v or 12V dc power supply with the right plug polarity availble. So no need for a full bridge design.

floobydust wrote:

- 16V8 PLD: I would recommend using the 22V10 instead. It has more lines and would be a better glue chip. I used one in my C02 Pocket SBC and my Github page has the schematic and code for it.

I have a couple of 22V10 and 18V8 here. So i can change this any time. But this is my first cpld aproach. I like KISS.

floobydust wrote:

- R65C51: This is a very old design, really for modems. Note that the older Rockwell parts are not easily found, much less in the higher 4MHz versions. Also note that the recent WDC W65C02 part has a defect with the transmit bit in the status register - there's a long post on the forum here that covers that in gory detail. Using a newer UART/DUART would be a better choice. I (and several others) have switched to NXP chips, mostly the SC28L92 DUART which has two serial ports and a counter/timer.

SC28L92 is only avaible in non DIL packages...
i had a some R65xxx already in stock, so i would like to use them.

floobydust wrote:

Also, when coding the PLD, it's best to keep the chip select lines decoded only using the address lines from the CPU. You do need to qualify the Write (and Read) signals for memory and other device to Ph2 clock. Using the 22V10, you can have qualified Read and Write signals, RAM and ROM select lines and 5- I/O selects that are 32-bytes wide.

i got the idea from Garth 6502 primer. http://wilsonminesco.com/6502primer/addr_decoding.html
All the /CS lines there are qualified with Phi2. I simply put this in CPLD code.

floobydust wrote:

...use a DS1813 as an NMI trigger with a momentary switch to trigger a Panic routine.

thats a nice idea.

floobydust wrote:

If you use a larger RAM chip, you can easily change your memory map (just recode the PLD) to get more contiguous RAM memory if needed. Also, where you decode your I/O can make a difference in how you can manage your memory mapping. I always use Page $FE for hardware I/O. This allows a more flexible memory map for contiguous memory.

In the first designs my io page was located at dxxx, like the c64. But i switched to the actual layout, because i have 128MB Flash (SST39SF010SA), which i want to use as ROM. Than i can have 8 different pages for Kernel ROM. And i have another 12KB addressspace for some kind of interpreter or programming.

floobydust wrote:

FInally, best of luck on getting your SBC up and running... there's lots of expertise out here... just ask if you have any questions... and have FUN!

I will do that. Thanks for your feedback.

[GARTHWILSON]

willie68 wrote:

I had a some R65xxx already in stock, so I would like to use them.

I've used a few different non-WDC brands of 65c51 and never had any trouble with them. In BillO's tests of several different brands all marked 2MHz and 4MHz, they all worked at 8MHz and some at 14MHz and even 19MHz. The only thing I don't like about the 65c51 design is that there are functions that ideally would have been separated, rather than merged, in their controls. It has never been a problem in my uses though. Separating them would have required another register, which would not fit in the scheme with only two register-select lines. I use the '51 regularly up to 115,200bps. The 6551 (non-CMOS) does have one thing I consider to be either a bug or a really idiotic design. I describe these things in my RS-232 (TIA-232) primer here and in the last have of the 6502 primer's page on I/O ICs here. I'm planning on using the SPI-interfaced MAX3100 UART for one I'm slowly working on now. I mention it since you're planning on having an SPI anyway for possible use with keyboard and display. There are tons of ICs on the market that use SPI and I²C.

Quote:

I got the idea from Garth's 6502 primer. http://wilsonminesco.com/6502primer/addr_decoding.html
All the /CS lines there are qualified with Phi2. I simply put this in CPLD code.

Make sure the 65xx I/O ICs' chip-select lines are not qualified by Φ2, and that whichever way you do the RAM, you cannot write to it while Φ2 is down.

Unless you already have something to plug into your expansion port, let me recommend distributing the power and ground connections along the length, for better AC performance, so any given signal's return current path is closer, rather than having to go clear to the end of the connector. The even distribution is all benefits, no disadvantages. I'll put a diagram about that in the 6502 primer. It's also good to arrange the power and ground connections such that if a board gets plugged in backwards, the power and ground still come out correctly so you're less likely to damage things.

[willie68]

GARTHWILSON wrote:

I'm planning on using the SPI-interfaced MAX3100 UART for one I'm slowly working on now. I mention it since you're planning on having an SPI anyway for possible use with keyboard and display. There are tons of ICs on the market that use SPI and I²C.

I'll keep this in mind, as the next "Generation" will have a dedicated SPI Interface.

GARTHWILSON wrote:

Make sure the 65xx I/O ICs' chip-select lines are not qualified by Φ2, and that whichever way you do the RAM, you cannot write to it while Φ2 is down.

Yes, thats part of the CPLD. Only RAM /CS will have Φ2 involved.

GARTHWILSON wrote:

Unless you already have something to plug into your expansion port, let me recommend distributing the power and ground connections along the length, for better AC performance, so any given signal's return current path is closer, rather than having to go clear to the end of the connector. The even distribution is all benefits, no disadvantages. I'll put a diagram about that in the 6502 primer. It's also good to arrange the power and ground connections such that if a board gets plugged in backwards, the power and ground still come out correctly so you're less likely to damage things.

At this moment the "Bus" is only something to put an Flash with ZIF socket on it. Nothing more.
For the other Bus i like the Idea of using edge card connector, like in the C64, with an asymetrical spacer in. The PCBs than only have a small slot milling on the "socket". But that's for later. Now the first prototype has to be up and running. Had to rewire all the address lines on the breadboard yesterday because a few lines were broken.

[willie68]

BTW.: I was thinking about another option to implement an UART.
Using an arduino pro micro. As interface between micro and SBC SPI will work. pro micro, because the USB Interface is already implement, too. And its available in a small formfactor. (And i have some here )

[BigEd]

(I've a feeling qualifying the RAM's write enable with phi2 might be preferable. But if so, maybe only when pushing the clock speed, and to do that you need also fast peripheral chips, so it might be out of scope.)

[willie68]

At the moment i'm at 1 MHz. Possible going to 2Mhz.
But what you mean is, /CS for RAM without Phi2 involved and the R/W is with Phi2 or should i combine /OE with Phi2 (only for the RAM)?

[willie68]

So, you mean something like this?

Code: Select all

header:
Name     W6502SBC_16 ;
PartNo   01 ;
Date     05.08.2022 ;
Revision 01 ;
Designer wkla ;
Company  nn ;
Assembly None ;
Location  ;
Device   G22V10 ;

pld:
/* *************** INPUT PINS *********************/
PIN 1   =  PHI2; 
PIN 2   =  A15;
PIN 3   =  A14;
PIN 4   =  A13;
PIN 5 	=  A12;
PIN 6 	=  A11;
PIN 7 	=  A10;
PIN 8 	=  A9;
PIN 9   =  A8;
//PIN 10  =  nn;
PIN 11  =  RW;
//PIN 13 	= nn; 

/* *************** OUTPUT PINS *********************/
PIN 23   =  CSRAM;
PIN 22   =  CSHIROM;
PIN 21   =  CSEXTROM;
PIN 20   =  CSIO;
PIN 19   =  CSIO0;
PIN 18   =  CSIO1;
PIN 17   =  CSIO2;
PIN 16   =  CSIO3;
PIN 15   =  MWR; // /WR only for RAM
PIN 14   =  MRD; // goes to all /OE of ROM and RAM

FIELD Addr = [A15..A8];

CSRAM = ! (Addr:[0000..7FFF]); // 32KB
CSIO = ! (Addr:[B000..BFFF]); // 4KB
CSIO0 = ! (Addr:[B000..B0FF]);
CSIO1 = ! (Addr:[B100..B1FF]);
CSIO2 = ! (Addr:[B200..B2FF]);
CSIO3 = ! (Addr:[B300..B3FF]);
CSEXTROM = ! (Addr:[8000..AFFF]); // 12KB
CSROM = ! (Addr:[C000..FFFF]);  // 16KB

MWR = ! (PHI2 & !RW);
MRD = ! (PHI2 & RW);

simulator:
ORDER: A15, A14, A13, A12, A11, A10, A9, A8, RW, PHI2, CSRAM, CSIO, CSIO0, CSIO1, CSIO2, CSIO3, CSEXTROM, CSHIROM, MWR, MRD; 

VECTORS:
/* RAM */
0 X X X X X X X 0 0 L H H H H H H H H H
0 X X X X X X X 0 1 L H H H H H H H L H
/* IO */
1 0 1 1 0 0 0 0 X X H L L H H H H H X X
1 0 1 1 0 0 0 1 X X H L H L H H H H X X
1 0 1 1 0 0 1 0 X X H L H H L H H H X X
1 0 1 1 0 0 1 1 X X H L H H H L H H X X
1 0 1 1 0 1 X X X X H L H H H H H H X X
1 0 1 1 1 X X X X X H L H H H H H H X X

/* 8000-AFFF external Rom */ 
1 0 0 0 X X X X X X H H H H H H L H X X
1 0 0 1 X X X X X X H H H H H H L H X X
1 0 1 0 X X X X X X H H H H H H L H X X

/* ROM */
1 1 X X X X X X 1 0 H H H H H H H L H H
1 1 X X X X X X 1 1 H H H H H H H L H L
1 1 X X X X X X 0 0 H H H H H H H L H H
1 1 X X X X X X 0 1 H H H H H H H L L H

[Dr Jefyll]

The number one rule, already mentioned by Garth, is that writes to memory must not occur while Phi2 is low. And it's also good (though less desperately important) if reads from memory cannot occur while Phi2 is low.

You have a choice regarding how to proceed. If you qualify the memories' Chip Select inputs with Phi2 then you will automatically satisfy both of the considerations mentioned above (because the chip can neither read nor write when CS is withheld). Qualifying the memories' Chip Selects with Phi2 may result in a very slight speed penalty, but speed is not a concern in your case!

The other way to proceed is to qualify the memories' /WR inputs (and preferably also the /RD aka /OE inputs) with Phi2.

Reminder: these remarks pertain to memory devices. 65xx I/O devices must never have their CS inputs qualified by Phi2 (as Garth already said).

ps- I see you've posted while I was typing. Do your equations conform to what we've been saying? Forgive me if I don't take the time to check!

-- Jeff

[BillO]

CUPL code looks good at fist glance.

[willie68]

Thanks all of you. I'll try the new pld on breadboard, if this ever works...