Hello!
I'm building a mostly simple SBC with the 6502, which I plan to get manufactured into a PCB and assemble myself into a working computer. I've made the schematic by using a few ideas from other people's projects on this forum and also from youtube videos like Ben Eater's and George Foot's videos.

This is my first time posting here but I've used this forum to gather ideas for my project for a while.
Below are some of my goals for this project. I'm looking for some reviews/sanity checks from people who have done this sort of thing before.

My goals for this build
The main thing I want to be able to do with this SBC is to program it with itself. This means having some way to input text from a keyboard and display it to some kind of screen/output device, and I've chosen a VGA monitor for this. I'm not trying to keep this compatible with the ROMs/BIOSs or code of old but I want to be able to write my own, preferably on the machine itself. Of course I'll need to write the ROM on a different PC and write it to the EEPROM.
[EDIT](Also, I dont want to use discrete logic for everything since I have some experience with trying to make that work. I've used an FPGA (the smallest one I could find, the same one that TinyFPGA uses) for the glue logic on this board and I plan to program the logic into that chip (via a JTAG header). I'm also not necessarily using all DIP chips because of lack space, and going SMD isnt that much of a problem so I think it will be a fun challenge too. -> Turns out this is harder than I thought and keeping it simple will help a lot)

To store programs on a sort of "disk", I thought I need to add some sort of serial interface which can talk to a SD card reader module, such that the computer can use it as storage like so: 6502 -> (ACIA, currently 6551) -> SD card module serial inputs. Now I'm not sure if this will work or if this is even possible with the hardware I have, but I have seen it done before.
The peripheral interface talks to a USB controller and should be able to use a USB keyboard as input device. This idea was taken from the schematic of the SBC dev board that WDC sells https://wdc65xx.com/Single-Board-Computers/w65c02sxb/ and I have used the same controller in almost the same config as them.

The video signal is being generated by a microcontroller (STM32) because I thought that's probably the easiest way to get it working without worrying about a lot of VGA signal timing. This MCU is fast enough to generate a 640x480 screen and has enough memory to store the framebuffer. Some more details are in my schematic.

The parts I'm using

uProcessor: W65C02S
ROM and RAM: AT28C256 and AS6C62256, both 32K
Glue logic: [EDIT](Lattice MachX02 256LUT FPGA -> NAND gates from Garth's Primer, for simplicity)
VIA: W65C22
[EDIT](ACIA: W65C51 -> Removed)
USB I/f: FT245RL
Video: [EDIT](STM32 F301 uController -> PIC32 MX270 because STMs are nowhere to be found)

Questions and Doubts

1. I am unsure if the configuration of ACIA and VIA I have, will work for interfacing with the computer. I've seen many people use the 6522 VIA to control the 6551 ACIA as a peripheral but i dont know if that is a requirement or can the ACIA act directly as a MMIO device?

2. My goal for the serial interface is to be able to connect some kind of SD card reader with a serial output to it and use that to load programs onto the computer. Since the W65C51N is in short supply from the suppliers I'm using, I am looking to swap it for a more modern chip that can do the same sort of job with roughly the same inputs and outputs. What, if any, are my options here?

3. Is the USB interface idea going to work? I know modern keyboards use different protocols from the PS2 keyboards which will just give you the scan code.

4. In the 6522 VIA I'm using, I have used port B as the data port and port A as a control port. I was planning to use two MSBs from Port A as a chip select so i can maybe have multiple peripheral devices. Is this a good idea? Chips like the USB interface dont have a Chip Select nowadays

If anyone can review these things and tell me if I'm doing something wrong, that'd be very helpful!
I have attached my schematic here for reference so that you can see the whole design.

The rest of the KiCAD project is on Github if you want to take a look at the PCB design or anything else: https://github.com/zrthxn/8puter
Thanks a ton!

Welcome and good luck!


I'm always very interested in people's video solutions, I'll check the schematic later.


I'm not sure what the benefit would be of interfacing it through the 6522. Maybe it allows faster CPU clock speeds without needing a faster 6551. It's fine if that's what you need, but probably more complex to program this way around. My personal default would probably be to just hook it to the main bus.


I'm not sure about this bit, I've never seen a 6551 used to drive an SD card and would have thought it not a good match. SD is mostly SPI, which has a separate clock line. You can bit-bang it quite easily on a 6522, and it is possible to use the internal shift register and/or one or two external ones to remove some load from the CPU in the process. That's what I would recommend and I have an implementation on GitHub that walks you through this setup and ends up with code to read arbitrary files from FAT32.

It also wouldn't take much to interface with 74-series logic, if 6522s are hard to get. Probably just two shift registers and a control module, and you could probably integrate it into your FPGA I should think if you know what you're doing there.


I don't know much about it but assuming the interface handles all the details of the USB HID communication with the keyboard, the practicality from your perspective really depends on what interface it provides to you, e.g. some form of serial or parallel interface would be easy, SPI would be nice too. I would have thought your side wouldn't need to know about USB at all.


Garth's primer has a great example of using one port to activate devices and sharing the other port to communicate with them all. I think that's what you mean? You can use something like a 74HC138 to decode three bits into 8 device select lines. You can also use the remaining pins of Port A to drive an addressable latch for more output bits if you need them - there are a lot of options depending how wide you need to go.

I would add a couple comments:

1- The WD65C51 has a known bug with the Xmit bit stuck on in the status register. There are workarounds, but I'd suggest going with a NXP SC28L91/92 UART/DUART instead. It's more programming effort to make it work, but a much better solution.

2- The FPGA datasheet implies the I/O pins are only compatible with 3.3V and lower voltage levels. You're mixing 5V logic with the FPGA, and the datasheet shows a maximum tolerance of 3.6V.

Lastly, if this is a first computer build project for you, perhaps scale it down and start with something simpler and less complex. That will make it easier to resolve issues when first trying to get it working.

_________________
Regards, KM
https://github.com/floobydust

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Re: floobydust


Yes I read about this in other discussions here, I think I'll replace it with something that can provide an SPI interface, maybe a CPLD, since I dont really know what I'd do with a UART. With SPI I could connect an SD card reader.


I had completely overlooked this! Fortunately the chips to which this FPGA is connected can tolerate 3.3V input high level, I checked all of them. But the FPGA itself cant tolerate the 5V from the 6502. It'll need some level shifters for that.

I think I'll avoid the whole FPGA idea since its too complex anyway and yet another thing to get wrong, and just go with very simple address decoding.
Thanks a lot!

You might want to look at using a GAL for soaking up a few "glue" chips and address decoding. I use a single 22v10 in my Ruby 6502 and 2 in my '816 board. Being older devices, they run at 5v.

-Gordon

_________________
--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

Re: gfoot

Thanks, you've made it a lot clearer for me.


I was wrong about that, my setup would not work for that. I'm thinking of using this 65SPI https://sbc.rictor.org/65spi2.html, using a CPLD, if I can figure that out.


The interface I'm using provides a parallel output so that can just directly go to the data bus, I think. Although since USB is a pretty complicated protocol I'm not sure if there's some software handshaking that needs to be done.

Something I'm still struggling with is, how would the 6522 know if the device on any particular port has finished putting data on the port? For example, the USB interface chip I'm currently using has two lines, ~RD and WR, which indicate when the parallel output is available. But how would the 6522 know this so it can trigger an interrupt?

I was asking bout this myself recently - you might want to have a look at this thread:

viewtopic.php?f=4&t=7065

and while I've since changed tack slightly since then, the CH375 device is the thing I'll be looking at when I get back to it.

-Gordon

_________________
--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

Re: GARTHWILSON

Thanks for your clarification! I was mixing up sync and aysnc serial protocols thinking its all serial

That seems very promising! I think I'll try to figure this out and have a SD card slot on the board itself.

I have seen this, although I would prefer to not have to bit-bang, having a dedicated chip for SPI might free up the 6522 to be used for other tasks at the same time, right?

Re: drogon

Thats a good idea too! I'll check if 22V10 chips are available, they'd probably be better for more complicated memory maps

Thanks! I'll look into that as well

Just a reminder that the 6502 (unless it's NMOS) doesn't need to run on 5V. You won't require level shifters if you have a 65C02 running at 3.3V.

Complicated memory maps aren't necessary, either. I'm not arguing against 22V10s (or against level shifters) -- they each make sense in certain contexts. You need to decide what's appropriate for this particular project.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Re: Dr Jefyll
You're right about running the whole system at 3.3V, it would make the FPGA functional. But unfortunately the EEPROM can only tolerate a main voltage of 4.5V and having just data lines regulated would be too much effort.

Update
Using the 65SPI CPLD design (https://sbc.rictor.org/65spi2.html), I've come up with this.
Buffer takes care of the 5V to 3.3V conversion.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Ah yes silly mistake !

By the way, the CPLD used in this 65SPI project, the Atmel ATF1504 is turning out to be a bit hard to find. Do you think the same program could be replicated on a Lattice CPLD? (thinking of M4A3-64/32)
Datasheet: https://www.mouser.in/datasheet/2/225/l ... 174572.pdf