65816 build -- completely stuck -- please help :)

[rehsd]

Hi, everyone! This is my first post to this forum. I'm glad to be part of this community!

I am trying my best to get a 65816 system up and running. Unfortunately, I am running into some issues, likely timing related. I could use some pointers. I have posted some background information here: https://www.rehsdonline.com/post/troubl ... ram-part-2.

The short version is that I am unable to get my ROM+RAM working with decoding logic. I'm guessing that I have a timing issue, but I haven't been able to figure it out.

I'd greatly appreciate any assistance you can provide.

Thanks!

Update: This issue has been resolved. Many updates were made based on great advice from members here. Ultimately, my lousy assembly coding was at fault. Credit to Adrien Kohlbecker for catching the issue with my code.

[GARTHWILSON]

Welcome.

Your linked page comes up for me for one or two seconds and then goes blank. I guess there's something there that doesn't like my older ff browser version on this computer. I hope to have my regular desktop computer setup working again this week. Note that you can attach images here, so it's not necessary to link to outside image hosts.

A couple of topics that might prove helpful are:

• Managing the 65816 multiplexed bus
• Jeff Laughton's animated visualizations of timing margins These excellent, drawn-to-scale (unlike most in data sheets) .gif's help understand what timings are constant and what varies with clock speed. Discussion about them is in the forum topic here

Also, go through the 6502 primer. It's not '816-specific, but most of the material there will apply anyway.

[banedon]

rehsd wrote:

Hi, everyone! This is my first post to this forum. I'm glad to be part of this community!

I am trying my best to get a 65816 system up and running. Unfortunately, I am running into some issues, likely timing related. I could use some pointers. I have posted some background information here: https://www.rehsdonline.com/post/troubl ... ram-part-2.

The short version is that I am unable to get my ROM+RAM working with decoding logic. I'm guessing that I have a timing issue, but I haven't been able to figure it out.

I'd greatly appreciate any assistance you can provide.

Thanks!

Looking at the your diagram, you don't seem to be utilising the VDA and VPA pins on the 65816. These are used to determine if there is a valid address on the address bus or not. A rule of thumb is a 1 on either or both is fine. 0 on both means an invalid address and should be ignored by the decoding circuitry. Page 15 of the datasheet has some information on this (section 2.26).

Recommendations
- Put VDA and VPA through an OR gate - either a specific OR gate IC or within a GAL/CPLD - and use that as a part of the enable for all of the address decoding. Without this you're going to have some really random stuff happen and it might be the main cause of your issue.
- When writing to RAM, validate it with PHI2 (main clock) so the write enable signal for the RAM is enabled only when PHI2 goes high. Never do this for any 65xx device though (such as the 6522 or 6551) as they expect to be fed the 65816's RWB output. Also, don't do this for the chip selects - they can be enabled as soon as you know VDA & VPA are valid and the address range matches.
- With regards your pull up resistors on the 65816: I suspect 1K is fine, but you could try a 2K2 or 3K3 (I use 3K3 in my designs) as it will do the job, but consume less current.
Also, is there a reason for 10K value on the BE line pullup resistor? I've not seen anyone use a different value to the other 65816 pull ups, which is why I ask.
- RESB might be better with a 3K3 pull up as it can be a little unreliable without it -something I was warned about and I have definitely seen on my 65C02 designs.

[Dr Jefyll]

Welcome!

Does your build still look like this (below)? If so, you have <ahem> some tidying up to do!

It's not just a matter of the length of all those cables. It also matters (a lot!) how the power and ground pins of your IC's get interconnected. For starters, cables between boards need to include at least one ground conductor (and ideally a power conductor too), attached to the local ground/power at each end. There are other requirements, too.

You mentioned you've been following Adrien Kohlbecker's video series, and he's facing some of the same issues. Have a look at the latest posts in his thread, here.

Given the fact that your project almost works, or works sometimes, it may seem to you as if only a minor tweak is needed. But that's misleading, as extensive changes may be necessary before you achieve solid, reliable operation. A project that works but is flaky can require just as much additional effort as one that's dead in the water. Sorry -- I don't make the rules, I'm just tellin' ya how it is!

banedon wrote:

- When writing to RAM, validate it with PHI2 (main clock) so the write enable signal for the RAM is enabled only when PHI2 goes high. Never do this for any 65xx device though (such as the 6522 or 6551) as they expect to be fed the 65816's RWB output.

This. But I wouldn't worry about pullup values. Ditto with the VPA, VDA thing, as problems in that department tend to be very subtle (not like what you're facing).

BTW your "schematic" is little more than a net list. It may seem clear to the person who created it, but others usually find it opaque -- it takes time to connect the dots. And not everyone will grant you that time. A real schematic with actual lines will increase the quantity and quality of the assistance you can garner here. Just sayin'!

-- Jeff

[rehsd]

GARTHWILSON wrote:

A couple of topics that might prove helpful are...

Thanks, @GARTHWILSON. I will spend some time going through these resources.

[rehsd]

banedon wrote:

Recommendations
- Put VDA and VPA through an OR gate - either a specific OR gate IC or within a GAL/CPLD - and use that as a part of the enable for all of the address decoding. Without this you're going to have some really random stuff happen and it might be the main cause of your issue.
- When writing to RAM, validate it with PHI2 (main clock) so the write enable signal for the RAM is enabled only when PHI2 goes high. Never do this for any 65xx device though (such as the 6522 or 6551) as they expect to be fed the 65816's RWB output. Also, don't do this for the chip selects - they can be enabled as soon as you know VDA & VPA are valid and the address range matches.
- With regards your pull up resistors on the 65816: I suspect 1K is fine, but you could try a 2K2 or 3K3 (I use 3K3 in my designs) as it will do the job, but consume less current.
Also, is there a reason for 10K value on the BE line pullup resistor? I've not seen anyone use a different value to the other 65816 pull ups, which is why I ask.
- RESB might be better with a 3K3 pull up as it can be a little unreliable without it -something I was warned about and I have definitely seen on my 65C02 designs.

Thanks, @banedon.

I will incorporate VDA and VPA. I hadn't as the sample schematic from WDC didn't seem to use it. My bad.

I will qualify the RAM's WE# with PHI2.

The pull-up resistor values were inaccurate on the schematic. I am using 3.3K the pull-ups, other than RESB, which uses a 1K (I could change it to a 3.3K). I will update the schematic. I have attached the reset circuit I am currently using.

[rehsd]

Dr Jefyll wrote:

Does your build still look like this? ....

No, it doesn't. I've attached a pic of my current PCB from which I'm working.

Dr Jefyll wrote:

BTW your "schematic" is little more than a net list. It may seem clear to the person who created it, but others usually find it opaque -- it takes time to connect the dots. And not everyone will grant you that time. A real schematic with actual lines will increase the quantity and quality of the assistance you can garner here. Just sayin'!

I appreciate the feedback on the schematic. I will post an updated version shortly.

Thanks!

[plasmo]

Redrew your schematic before your last two updates. It should be easier to analyze by the guys here. I don't see anything wrong specifically, but AC or ACT components are dangerous; too fast, too noisy. 15nS RAM is also bad news.
Bill

[banedon]

Dr Jefyll wrote:

banedon wrote:

- When writing to RAM, validate it with PHI2 (main clock) so the write enable signal for the RAM is enabled only when PHI2 goes high. Never do this for any 65xx device though (such as the 6522 or 6551) as they expect to be fed the 65816's RWB output.

This. But I wouldn't worry about pullup values. Ditto with the VPA, VDA thing, as problems in that department tend to be very subtle (not like what you're facing).

I mentioned the pull ups as a suggestion more than anything else, not to resolve the issue at hand .

[rehsd]

plasmo wrote:

Redrew your schematic before your last two updates. It should be easier to analyze by the guys here. I don't see anything wrong specifically, but AC or ACT components are dangerous; too fast, too noisy. 15nS RAM is also bad news.
Bill

I have attached my updated schematic (before the pending updates based on feedback above). This isn't as nice as what you drew, Bill.

I have tried the circuit with all HC / HCT. Is that a better way to go?

Also, what should I look for in RAM?

Thank you!

[barrym95838]

plasmo wrote:

I don't see anything wrong specifically, but AC or ACT components are dangerous; too fast, too noisy. 15nS RAM is also bad news.

Kinda like installing a big V-8 in a go-cart? Doable, but likely to cause problems, some obvious and others not so obvious ...

[akohlbecker]

barrym95838 wrote:

plasmo wrote:

I don't see anything wrong specifically, but AC or ACT components are dangerous; too fast, too noisy. 15nS RAM is also bad news.

Kinda like installing a big V-8 in a go-cart? Doable, but likely to cause problems, some obvious and others not so obvious ...

Unfortunately, the 65C816 requires an AC chip for at least the bank address latching as well as the associated logic, as the timing margin is pretty thin (10ns to latch after rising edge of clock).

rehsd wrote:

I have tried the circuit with all HC / HCT. Is that a better way to go?

Also, what should I look for in RAM?

Thank you!

Having as less as possible AC/ACT chips on a breadboard is the way to go. On a PCB I would say it is fine if you have proper signal return paths / ground planes. Can you share screenshots of your PCB routing?

For the RAM, go with a slow, 55ns one before attempting to increase the speed. This goes for all the components, if they don't have a reason to be fast, go with slow chips, as they will be easier to manage for a start. Once you have a working slow build, then you can try to increase speed.

Your GAL can also be an issue with fast edges. Which model are you using? Can you also share how you're programming it and with which equations?

banedon wrote:

- Put VDA and VPA through an OR gate - either a specific OR gate IC or within a GAL/CPLD - and use that as a part of the enable for all of the address decoding. Without this you're going to have some really random stuff happen and it might be the main cause of your issue.

Having VDA, VPA be a part of the address decoding works but I would argue it is better to incorporate it into the read-write pulses. This way the address decoding is a fully static look-up, and you can more easily do DMA. Either way, I agree that they need to appear in the logic. I just released an episode on that subject yesterday, coincidentally!

[GARTHWILSON]

akohlbecker wrote:

Unfortunately, the 65C816 requires an AC chip for at least the bank address latching as well as the associated logic, as the timing margin is pretty thin (10ns to latch after rising edge of clock).

The 74HC573's required input data hold time is guaranteed to be no more than 5ns, and 2ns is typical. My 74AC data book is not clear on this, but it appears to be saying that the data input could even start to change up to a whole nanosecond before the latch enable, and it would still keep the right value at the output.

Quote:

For the RAM, go with a slow, 55ns one before attempting to increase the speed.

I think what we're talking about here is output edge rate, rather than access time. They're two separate things. Without looking through a lot of data sheets again, I don't remember ever seeing the output edge rates specified on SRAMs. Have you?

[BigDumbDinosaur]

rehsd wrote:

Hi, everyone! This is my first post to this forum. I'm glad to be part of this community!

Welcome! Glad to read that the 65C816 is getting some much-needed love.

Quote:

I am trying my best to get a 65816 system up and running. Unfortunately, I am running into some issues, likely timing related. I could use some pointers. I have posted some background information here: https://www.rehsdonline.com/post/troubl ... ram-part-2.

Like Garth, I cannot view that page. You can attach schematics, pictures, etc., to your posts here and save readers the trouble of having to go off-site.

[BigDumbDinosaur]

plasmo wrote:

Redrew your schematic before your last two updates. It should be easier to analyze by the guys here. I don't see anything wrong specifically, but AC or ACT components are dangerous; too fast, too noisy. 15nS RAM is also bad news.
Bill

Ah! A schematic that is actually a schematic and, especially important to me, is not in color.

74AHC is a good choice, as it combines the speed of 74AC with the more “gentle” outputs of 74HC. I've used 74AC/ACT in all my designs to date without noise problems, but these are on four-layer boards with internal ground and power planes, and meticulous attention to layout details. 74AC/ACT on a two-layer board may be a pretty unforgiving arrangement due to ground bounce, ringing, etc.

No pullup resistor is required on RWB, as that output is driven in both directions—it's not an open-collector output.