6502 project

[akohlbecker]

Hey all,

While I'm still working on my 65C816 videos, those take time and the design doesn't happen as fast as when I'm working on my own. So I wanted to have fun and design a new motherboard for my 6502.

This is the current board I designed. You can find more info on it on my Github:

It works pretty well, but it is a bit cramped. I also wanted to move to SPLDs for the glue logic, and add the VIA directly to the PCB. So, enter this new board:

Here is the schematic

I made a few updates to the design:

- It is still using pin headers to plug into the breadboard, but this time only headers, not sockets, and with rearranged pins (don't need the full address bus, added the VIA ports instead)
- I switched to two ATF22V10 with ZIF sockets for the glue logic. It would fit in 16V8s but this is what I had on hand. The 22V10s are also more featureful (you can tri-state individual pins). I exposed the unused pins in the header on the right so I can play with them later
- I also added a new "debug" or "dma" IDC40 connector, which contains all the CPU signals, plus a couple of unused SPLD pins. I plan on using this for a bus monitor, or alternatively something based on Ben Eater's VGA card.
- The power section is slightly improved, with a non-reversible connector and a fuse
- the RDY and RST pins are now wire-ORed with a diode, to protect the components in case I decide to tie them high to VCC with a jumper or something (which already happened once on the old board)
- the built-in oscillator is 4Mhz, and can be three stated by the debug device by pulling down the OSC_EN pin. So I can drive the clock with an Arduino for debugging

Finally here is the routing. I made so much progress with routing things cleanly since the previous board, I'm pretty pleased with the result. Board is 4 layers with 2 inner ground planes

The SPLD logic is quite simple:

Code: Select all

CLK = OSC;
CLK.OE = OSC_EN;

IRQ = !IRQ1 # !IRQ2 # !IRQ3 # !IRQ4;

READ = RW & (CLK # !RDY);
READ.OE = BE;

WRITE = !RW & (CLK # !RDY);
WRITE.OE = BE;

Code: Select all

IO = !A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7;

ROM_CS = A15;
RAM_CS = !A15 & !IO;

IO1 = IO & A6 & !A5 & !A4;
IO2 = IO & A6 & !A5 & A4;
IO3 = IO & A6 & A5 & !A4;
IO4 = IO & A6 & A5 & A4;

Hopefully, you find this interesting! Any suggestions before I send it to the fab?

[BigDumbDinosaur]

akohlbecker wrote:

Hopefully, you find this interesting! Any suggestions before I send it to the fab?

Not anything that should affect your PCB layout, but I suggest you reduce resistor network RN1 to 3.3K. Use of 10K will make the attached circuits noise-sensitive.

[akohlbecker]

BigDumbDinosaur wrote:

akohlbecker wrote:

Hopefully, you find this interesting! Any suggestions before I send it to the fab?

Not anything that should affect your PCB layout, but I suggest you reduce resistor network RN1 to 3.3K. Use of 10K will make the attached circuits noise-sensitive.

Interesting! I did notice you were using 3.3k in your projects, but I wasn't sure why. What is it about 3.3k that makes it less noise sensitive?

[drogon]

You don't need the pull-ups on signals that are driven, like the R/W, /Read, /Write and /Rom_WE ..

Looks good though - hope it works well!

-Gordon

[BigDumbDinosaur]

akohlbecker wrote:

BigDumbDinosaur wrote:

akohlbecker wrote:

Hopefully, you find this interesting! Any suggestions before I send it to the fab?

Not anything that should affect your PCB layout, but I suggest you reduce resistor network RN1 to 3.3K. Use of 10K will make the attached circuits noise-sensitive.

Interesting! I did notice you were using 3.3k in your projects, but I wasn't sure why. What is it about 3.3k that makes it less noise sensitive?

The higher the resistance, the easier it is for low-going noise to pull down the affected circuit and possibly trigger an unexpected response. In general, the lower the value of the pull-up resistor, the more noise-immune the circuit will become. Also, in the case of wired-OR circuits such as /IRQ, the lower the resistor, the smaller the circuit's R-C time-constant. A large time-constant will result in a circuit that is slow to return to the quiescent state, and in the case of /IRQ, may result in a spurious interrupt.

Obviously, going too low with the resistor will overburden any device pulling the circuit low. For many applications, 3.3K is a good compromise between reduced noise and current draw when the circuit is being driven low. In a 5 volt system, 3.3K will produce about 1.5 mA when the circuit is being driven low, which is safe with almost all devices. If your wired-OR circuits are being driven by 74AC or 74AHC logic, 1.0K is good and gives extra noise margin. Examining the sinking current rating of the device(s) connected to the pull-up resistor will help in selecting a suitable value.

drogon wrote:

You don't need the pull-ups on signals that are driven, like the R/W, /Read, /Write and /Rom_WE ..

I noticed that but didn't think to comment.

[akohlbecker]

drogon wrote:

You don't need the pull-ups on signals that are driven, like the R/W, /Read, /Write and /Rom_WE ..

Looks good though - hope it works well!

-Gordon

Thank you!

R/W is tri-stated by the CPU when BE is taken low. Similarly, I will tri-state /Read and /Write to allow the DMA device to generate its own pulses. In my case, my VGA card (based on Ben Eater's) relies on being able to set /Read after stopping the CPU. Which means there will be some interval when they will not be driven. I don't think it would be safe to leave them without a pull up? Or am I mistaken?

For /Rom_WE, this one is not being driven at the moment, so I want to pull it up but keep the ability to build a ROM programmer later.

BigDumbDinosaur wrote:

The higher the resistance, the easier it is for low-going noise to pull down the affected circuit and possibly trigger an unexpected response. In general, the lower the value of the pull-up resistor, the more noise-immune the circuit will become. Also, in the case of wired-OR circuits such as /IRQ, the lower the resistor, the smaller the circuit's R-C time-constant. A large time-constant will result in a circuit that is slow to return to the quiescent state, and in the case of /IRQ, may result in a spurious interrupt.

Obviously, going too low with the resistor will overburden any device pulling the circuit low. For many applications, 3.3K is a good compromise between reduced noise and current draw when the circuit is being driven low. In a 5 volt system, 3.3K will produce about 1.5 mA when the circuit is being driven low, which is safe with almost all devices. If your wired-OR circuits are being driven by 74AC or 74AHC logic, 1.0K is good and gives extra noise margin. Examining the sinking current rating of the device(s) connected to the pull-up resistor will help in selecting a suitable value.

That makes sense. I have to check the current ratings for the wired-OR RDY and RST inputs. Right now I'm using 1k because that's what gives me a fast return to 5V (measured around 30ns in my 65C816 videos).

For this board I already ordered the quite atypical 12 pin 10k resistor network so I'll solder it in, but I'll keep this suggestion in mind for the next one

[BigDumbDinosaur]

akohlbecker wrote:

drogon wrote:

You don't need the pull-ups on signals that are driven, like the R/W, /Read, /Write and /Rom_WE ..

R/W is tri-stated by the CPU when BE is taken low. Similarly, I will tri-state /Read and /Write to allow the DMA device to generate its own pulses. In my case, my VGA card (based on Ben Eater's) relies on being able to set /Read after stopping the CPU. Which means there will be some interval when they will not be driven. I don't think it would be safe to leave them without a pull up? Or am I mistaken?

Strange as it may seem, momentary floating isn't quite as deleterious it it would seem. The circuit's parasitic capacitance can cause bus state to persist for tens of microseconds, and sometimes longer (Garth discovered that whilst testing his memory modules). That said, pull-ups cause no harm—they only cost you in board space and power consumption when the circuit is driven low.

[akohlbecker]

BigDumbDinosaur wrote:

Strange as it may seem, momentary floating isn't quite as deleterious it it would seem. The circuit's parasitic capacitance can cause bus state to persist for tens of microseconds, and sometimes longer (Garth discovered that whilst testing his memory modules). That said, pull-ups cause no harm—they only cost you in board space and power consumption when the circuit is driven low.

That is good to know! Thanks for the tip


I'm considering replacing my diode+pull-up circuit for the RDY input with a simple series resistor. I think this would give me a better propagation delay of the RDY input going low to high.

Now, the gate driving the RDY input is a 74HC74 which can source 4mA. So this would mean I need a resistor ≥1.25k. However on the CPU side WDC's datasheet is not very clear, they're talking about a MIN I_ol of 1.6mA. Do you reckon there is a minus sign missing? Meaning it can't go lower than -1.6mA? Which would mean R≥3.125k

The 65C816's datasheet is even more confusing, they don't mention RDY, they confuse voltage and current, and the same number now is MIN 3.2mA, but there is also a MAX of 20mA What would the maximum mean in this case then?

Any help deciphering these figures would be much appreciated!

[drogon]

akohlbecker wrote:

Now, the gate driving the RDY input is a 74HC74 which can source 4mA. So this would mean I need a resistor ≥1.25k. However on the CPU side WDC's datasheet is not very clear, they're talking about a MIN I_ol of 1.6mA. Do you reckon there is a minus sign missing? Meaning it can't go lower than -1.6mA? Which would mean R≥3.125k

Remember that Rdy is an output as well as an input signal.

The CPU will drive Rdy low when you execute a WAI instruction. This is the mechanism I use to communicate with the ATmega host processor I use.

-Gordon

[BigDumbDinosaur]

akohlbecker wrote:

I'm considering replacing my diode+pull-up circuit for the RDY input with a simple series resistor. I think this would give me a better propagation delay of the RDY input going low to high.

A Schottky diode such as the attached has a reverse recovery time of 4ns. That is insignificant at the speeds you are running.

schottky_npx_bat85.pdf

BAT85 Small-Signal Schottky Diode.

(126.05 KiB) Downloaded 151 times

Quote:

Now, the gate driving the RDY input is a 74HC74 which can source 4mA. So this would mean I need a resistor ≥1.25k. However on the CPU side WDC's datasheet is not very clear, they're talking about a MIN I_ol of 1.6mA. Do you reckon there is a minus sign missing? Meaning it can't go lower than -1.6mA? Which would mean R≥3.125k

The 65C816's datasheet is even more confusing, they don't mention RDY, they confuse voltage and current, and the same number now is MIN 3.2mA, but there is also a MAX of 20mA What would the maximum mean in this case then?

74HC logic can reliably drive up to 8mA high or low. I would stay with 1K for RDY's pullup. Connect the diode's anode directly to RDY and the cathode to the 74HC74. You'll be fine.

[GARTHWILSON]

I just looked at the 816's data sheet from Oct 10, 2018, and couldn't believe it still has problems, after all this time, and all we've pointed out to WDC and they've corrected. The electrical characteristics on page 27 are apparently for the W65C22N (not S, let alone the '02 or '816)! [Edit: I see the 11/9/18 revision fixed this.] The 816's pin drivers are a lot stronger than the data sheet lets on though. I'm not sure how you plan to connect this resistor for the RDY line though. The diagram I'm seeing above shows the '02, not the '816. I suspect that you could eliminate the pull-up resistor and replace the diode with a resistor, maybe a 10K, and then to keep the RxC time constant from being a problem, put a 22pF or 47pF capacitor across it. There's no reason to go above 47pF. The capacitor will give you instant response without DC loading.

[akohlbecker]

drogon wrote:

akohlbecker wrote:

Now, the gate driving the RDY input is a 74HC74 which can source 4mA. So this would mean I need a resistor ≥1.25k. However on the CPU side WDC's datasheet is not very clear, they're talking about a MIN I_ol of 1.6mA. Do you reckon there is a minus sign missing? Meaning it can't go lower than -1.6mA? Which would mean R≥3.125k

Remember that Rdy is an output as well as an input signal.

The CPU will drive Rdy low when you execute a WAI instruction. This is the mechanism I use to communicate with the ATmega host processor I use.

-Gordon

Yes, that is the purpose of my circuit: by adding a series resistor between RDY and what's driving it, I prevent the short circuit that could occur when the CPU executes WAI

BigDumbDinosaur wrote:

akohlbecker wrote:

I'm considering replacing my diode+pull-up circuit for the RDY input with a simple series resistor. I think this would give me a better propagation delay of the RDY input going low to high.

A Schottky diode such as the attached has a reverse recovery time of 4ns. That is insignificant at the speeds you are running.

schottky_npx_bat85.pdf

Quote:

Now, the gate driving the RDY input is a 74HC74 which can source 4mA. So this would mean I need a resistor ≥1.25k. However on the CPU side WDC's datasheet is not very clear, they're talking about a MIN I_ol of 1.6mA. Do you reckon there is a minus sign missing? Meaning it can't go lower than -1.6mA? Which would mean R≥3.125k

The 65C816's datasheet is even more confusing, they don't mention RDY, they confuse voltage and current, and the same number now is MIN 3.2mA, but there is also a MAX of 20mA What would the maximum mean in this case then?

74HC logic can reliably drive up to 8mA high or low. I would stay with 1K for RDY's pullup. Connect the diode's anode directly to RDY and the cathode to the 74HC74. You'll be fine.

The way I understand this, once the flip flop goes from low to high, we are depending on the RC time constant of the RDY pin + pull-up, since the gate is disconnected.
I measured ~30ns to reach a valid logic level with a 1k pull-up, which is why I want to change this to a series resistor only. That way the flip flop can drive the pin high directly. Not sure if my understanding of how this diode circuit works is correct.

Basically, I'm trying to avoid the case where the flip flop going high isn't registered in the current clock cycle (because 30ns is near half the period).

GARTHWILSON wrote:

I just looked at the 816's data sheet from Oct 10, 2018, and couldn't believe it still has problems, after all this time, and all we've pointed out to WDC and they've corrected. The electrical characteristics on page 27 are apparently for the W65C22N (not S, let alone the '02 or '816)! [Edit: I see the 11/9/18 revision fixed this.] The 816's pin drivers are a lot stronger than the data sheet lets on though. I'm not sure how you plan to connect this resistor for the RDY line though. The diagram I'm seeing above shows the '02, not the '816. I suspect that you could eliminate the pull-up resistor and replace the diode with a resistor, maybe a 10K, and then to keep the RxC time constant from being a problem, put a 22pF or 47pF capacitor across it. There's no reason to go above 47pF. The capacitor will give you instant response without DC loading.

I'm considering the same change in my '02 and '816 projects which is why I'm talking about both

Can you tell me more about that capacitor? I'm not sure I understand what it does. How does it prevent the RC constant from being a problem?

[GARTHWILSON]

akohlbecker wrote:

Yes, that is the purpose of my circuit: by adding a series resistor between RDY and what's driving it, I prevent the short circuit that could occur when the CPU executes WAI

<snip>

Can you tell me more about that capacitor? I'm not sure I understand what it does. How does it prevent the RC constant from being a problem?

Here's the idea:

drivingRDY.gif (9.71 KiB) Viewed 1904 times

The resistor prevents the two outputs from fighting each other if the processor actively pulls RDY down. The shunt capacitor keeps the input capacitance of the RDY line (plus socket and PCB traces) from forming a pole and a time constant with the resistor. The signal from the flip-flop reaches the processor without delay. If the processor does pull RDY down while the flip-flop is outputting a high, the only load is the max of 110 picocoulombs of charge on the capacitor (if it's a 22pF) which will take place in a fraction of a clock cycle.

[akohlbecker]

Thanks! I was curious to see this in action so I made a simulation in CircuitJS

I took some values for the output and input capacitance of HC gates from TI's Designing With Logic.
The beginning of the trace is without the shunt capacitor, when the input switches, and the end of the trace is with the capacitor added. So looks like it works! Magic!

[drogon]

akohlbecker wrote:

drogon wrote:

akohlbecker wrote:

Now, the gate driving the RDY input is a 74HC74 which can source 4mA. So this would mean I need a resistor ≥1.25k. However on the CPU side WDC's datasheet is not very clear, they're talking about a MIN I_ol of 1.6mA. Do you reckon there is a minus sign missing? Meaning it can't go lower than -1.6mA? Which would mean R≥3.125k

Remember that Rdy is an output as well as an input signal.

The CPU will drive Rdy low when you execute a WAI instruction. This is the mechanism I use to communicate with the ATmega host processor I use.

-Gordon

Yes, that is the purpose of my circuit: by adding a series resistor between RDY and what's driving it, I prevent the short circuit that could occur when the CPU executes WAI

I never had a properly working system when I was trying to drive Rdy to stop the CPU. I did start a thread or 2 here about it too, but while it seems it should work it didn't for me, so I'm really keen to see your ideas - if it works.

see e.g. viewtopic.php?f=4&t=6743&hilit=rdy

In my systems it was to establish a communications method between the ATmega and the 6502/816. I resorted to a slightly different tact in that the ATmega MCU would never stop the 6502/816 CPU but the CPU would execute WAI causing it to stop at which point the MCU which was monitoring the Rdy line on an input pin would 'wake up', /BE the CPU, do a data transfer, un-BE it, then send it an interrupt to get it to carry on.

There are (were) issues with interrupts but I solved that in external logic. (inside a GAL)

Looking forward to seeing your systems using Rdy - hope it works well.

-Gordon