Hey all,
While I'm still working on my
65C816 videos, those take time and the design doesn't happen as fast as when I'm working on my own. So I wanted to have fun and design a new motherboard for my 6502.
This is the current board I designed. You can find more info on it
on my Github:
Attachment:
after.jpg [ 1.45 MiB | Viewed 1539 times ]
It works pretty well, but it is a bit cramped. I also wanted to move to SPLDs for the glue logic, and add the VIA directly to the PCB. So, enter this new board:
Attachment:
Screenshot 2021-11-08 at 20.46.07.png [ 3.73 MiB | Viewed 1539 times ]
Here is the schematic
Attachment:
Screenshot 2021-11-08 at 20.51.13.png [ 1.14 MiB | Viewed 1539 times ]
I made a few updates to the design:
- It is still using pin headers to plug into the breadboard, but this time only headers, not sockets, and with rearranged pins (don't need the full address bus, added the VIA ports instead)
- I switched to two ATF22V10 with ZIF sockets for the glue logic. It would fit in 16V8s but this is what I had on hand. The 22V10s are also more featureful (you can tri-state individual pins). I exposed the unused pins in the header on the right so I can play with them later
- I also added a new "debug" or "dma" IDC40 connector, which contains all the CPU signals, plus a couple of unused SPLD pins. I plan on using this for a bus monitor, or alternatively something based on Ben Eater's VGA card.
- The power section is slightly improved, with a non-reversible connector and a fuse
- the RDY and RST pins are now wire-ORed with a diode, to protect the components in case I decide to tie them high to VCC with a jumper or something (which already happened once on the old board)
- the built-in oscillator is 4Mhz, and can be three stated by the debug device by pulling down the OSC_EN pin. So I can drive the clock with an Arduino for debugging
Finally here is the routing. I made so much progress with routing things cleanly since the previous board, I'm pretty pleased with the result. Board is 4 layers with 2 inner ground planes
Attachment:
Screenshot 2021-11-08 at 20.50.32.png [ 2.01 MiB | Viewed 1539 times ]
The SPLD logic is quite simple:
Code:
CLK = OSC;
CLK.OE = OSC_EN;
IRQ = !IRQ1 # !IRQ2 # !IRQ3 # !IRQ4;
READ = RW & (CLK # !RDY);
READ.OE = BE;
WRITE = !RW & (CLK # !RDY);
WRITE.OE = BE;
Code:
IO = !A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7;
ROM_CS = A15;
RAM_CS = !A15 & !IO;
IO1 = IO & A6 & !A5 & !A4;
IO2 = IO & A6 & !A5 & A4;
IO3 = IO & A6 & A5 & !A4;
IO4 = IO & A6 & A5 & A4;
Hopefully, you find this interesting! Any suggestions before I send it to the fab?
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What would the maximum mean in this case then?
