Address Decoding

[MrLinuxGuy]

Hi everybody,
Long time no see. I've been very busy with schoolwork, and living in a country far away from any electronics stores and with an unreliable (as in usually 70% of packages are 'inspected') postage system, I had to put my electronics hobby on the side. However, over the past 2 weeks, I've had a lot of free time, so I finally got some of my act together, and have began designing an address decoder for my project. I have decided to have 4x32 kbyte SRAMs, an 8 kbyte 'bootloader' ROM, a 128 kbyte OS ROM, and a couple of I/O devices (such as an attiny for the keyboard and two VIA's). I have made a decoding circuit which involves 2 74138's, one 74139, and an an XNOR gate. Here is the schematic of the circuit as seen below (screenshot of a program):

6502.org wrote:

Image no longer available: http://img218.imageshack.us/img218/9021/decodingcircuit.jpg

Sorry for the confusing layout, but my scanner isn't working, and i was not able to scan the nice diagram I made... anyways, I've color coded the diodes, the green ones are the RAM, the red/purple ones the ROM, and yellow is the I/O devices. The gate with the '1' is a NOT gate, and the '=1' is a XOR gate.

Here is the address range i used in order to construct the circuit:

000000-007FFF RAM 1 (32 KB)
008000-00DFFF EMPTY (24 KB)
00E000-00FFFF boot ROM (8 KB)
010000-017FFF RAM 2 (32 KB)
018000-01FFFF RAM 3 (32 KB)
020000-027FFF RAM 4 (32 KB)
028000-037FFF Program slot 1 (64 KB)
038000-047FFF Program slot 2 (64 KB)
048000-067FFF O.S. ROM (128KB)
080000-0800FF VIA 1
080100-0801FF VIA 2
080200-0802FF AT Tiny (keyboard)
080300-0803FF AT Tiny (status lights on front panel)
080400-0804FF AT mega (video chip)
080500-0805FF AT mega (RS232 communications)

Unfortunately, I fear that since it is my first time designing such a thing, i have made the circuit too inefficient or have done something wrong with the way i designed it. I also am not sure how memory access works, the slowest chip i have has an access time of 120ns. I am wondering whether or not running at 4 Mhz will be appropriate, but I'm not sure how long it takes to read or write to memory, from what I understand, it allows a maximum (for 4 Mhz) 125 ns to do address decoding (and activate the chip), and another 125 ns to actually wait for the memory to spit out data.

Finally, if i use a latch, what latch should I use and how should I hook it up? I think that using the 74573 and hooking the pin to hold the output to phi2 is how i should do it, but i am not sure how to connect the data buses without causing interference to the address buses.

[GARTHWILSON]

I apologize that the following may not be very clear. It would be very time-consuming to write up a tutorial on examining timing diagrams and charts and applying them to a particular plan for address decoding and other glue logic (which may be why there have been no responses yet.

Quote:

it allows a maximum (for 4 Mhz) 125 ns to do address decoding (and activate the chip), and another 125 ns to actually wait for the memory to spit out data.

That's a little optimistic. Since you have A16 through A19, are you using the 65816? It looks like WDC's '816 data sheet is still a little messed up; but from the best I can make out there, the high address byte isn't guaranteed to be valid until 33ns after the cycle starts on a 14MHz '816, and you have to add the delay of your '573 to that, which for a 74HC573 is 19ns max, resulting in 52ns worst case. IOW, at 4MHz, you can't plan on having 125ns for address decoding. Now you have to add the propagation delay time of your '138, which is 41ns max for LS and 35ns max for HC. (Yes, HC is usually just a hair faster than LS.) 52ns+41ns=93ns taken out of your first 125ns. That's all worst-case, but you can't design around the typical times and not expect to have problems once in awhile. Note that the R/W\ line is also not guaranteed to be valid before A0-A15 are, so to avoid accidentally writing garbage to RAM addresses you're using, you can't have RAM enabled right away-- or at least don't have it go into write mode right away. The easiest way to avoid problems is to bring phase-2 into the RAM-enabling or into the RAM-write-enabling circuit. Your glue logic will take some time out of the 125ns of phase-2-high time, and so will the data set-up time required by the processor which I think is 10ns for the 14MHz part and 30ns for a 4MHz part. IOW, even 100ns RAM may not be fast enough for 4MHz. 70ns should be fine. After taking all the numbers from the timing charts for a particular speed and making your circuit, if you're only making one unit, you can experiment and use the highest anticipated temperature and lowest anticipated power supply voltage and run the clock speed up and see where the first thing starts to fail, then back the speed off a bit for reliability.

To get the address map you've specified, you will have an awful lot of logic levels in your address decoding, and that will put a lid on your top speed. See if you can factor it better. Since you have nearly the top half of the 16MB address space unused, you might be able to use that to your advantage and re-arange things. 138's and 139's are popular for obvious reasons but kind of slow because of their many levels of internal logic (4 to 5 delays each). The '154 with 16 outputs is about the same speed. A 6502 system can have 32KB of ROM and 16KB of RAM (or vice-versa) and up to ten 65xx I/O ICs (like VIAs and ACIAs) using just three sections of a single 74xx00 quad NAND gate for all the address decoding. This is what I have on my workbench computer, with the scheme shown at http://www.6502.org/users/garth/project ... chematic=2 . (Actually it has 3 VIAs and 3 ACIAs.) It uses individual address lines for one of the select inputs for each I/O IC. It makes the IC addressable at more than one address, and will also allow addressing more that one IC at a time if you don't use the right address, but in my 15+ years of using this computer, that has never been a problem.

Quote:

Finally, if i use a latch, what latch should I use and how should I hook it up? I think that using the 74573 and hooking the pin to hold the output to phi2 is how i should do it, but i am not sure how to connect the data buses without causing interference to the address buses.

If things are not enabled to output data to the bus before phase-2 rises, you should be fine. I see WDC just put the '245 bus transceiver in their figure 5-1 of the data sheet, but this is rather new. They went without it for the first two decades.

[ElEctric_EyE]

MrLinuxGuy wrote:

Finally, if i use a latch, what latch should I use and how should I hook it up?... .

I like to use the '573 for a latch to read data from a "device", and the '574 to write data. The '574 can be used as a port, usually the /OE is grounded, and on the low to high transition (of say an active high address select) of the LE pin, the data will be "latched" to the output pins, until the next low to high transition. The '573 is a "transparent" latch. In it's case, to make it transparent, LE must be held high. When an address select (active low) is present on the /OE pin, it will transfer data from the D inputs to the Q outpus. Hope this helps.

P.S. I do not understand your drawing.

[MrLinuxGuy]

I hope no one will get angry at me for reviving such an old thread, but a lot of things have happened since then and now, leaving me little time for my interest in electronics (such as taking my IB exams, deciding where to go for university, and finding a future place to live).
I was still looking at a way around to do address decoding, when i stumbled upon Lee Davidson's 6502 SBC http://members.lycos.co.uk/leeedavison/ ... index.html, and saw that he uses a GAL to do address decoding. Wouldn't it be easier to use a GAL or a CPLD to decode addresses? It would definitively remove the need for several logic chips, and does provide reasonable propagation delays (no greater than 12ns for the Lattice one). It would also be reprogrammable, allowing the system to be changed if necessary. I will admit that it is more expensive than just using a 7400 series chip though. Doesn't the SBC-3 use its main FPGA to do adress decoding as well?

Thanks!

PS: if you want to start a new thread, just tell me, I'm not sure whether or not i should start a new one on the same subject or reuse this one)

[GARTHWILSON]

Quote:

PS: if you want to start a new thread, just tell me, I'm not sure whether or not i should start a new one on the same subject or reuse this one)

No, please keep related stuff together, keeping the forum less cluttered, and saving time by eliminating the need to re-hash something just because it's not in the same thread when it could have been. Since we work on this stuff in our spare time, some projects may take years, and we don't want to re-start a topic every time we get a little more time on it just because the last post was a few months ago.

[8BIT]

Yes, it is easy to do and requires less chip space, and my SBC-3 does use the large CPLD and the smaller CPLD to decode addresses.

Some downsides are:
it requres special programming tools (expensive)
is not easy for beginners to understand how the decoding works
relies on parts that may not be available in the future

It boils down to your personal preferences. I feel as long as the logic equations are made available, then replicating it to other devices is possible. I also feel that in the not-too-distant future, the old standard logic chips will not be produced any longer. Yes, you will be able to still find them, but there will not be any new ones produced. (Just my personal opinion).

Daryl

[Bramblefax]

Do you really think there will ever stop being a market for something as ubiquitous as nand gates, flip flops, or decade counters? I see such a future being a long way off, even if it does mean us hobbyists' beloved wire-wrap-able, dead-bug-able DIP-style 74xxx chips aren't available, I would think something similar would take their place.

[BigDumbDinosaur]

8BIT wrote:

I also feel that in the not-too-distant future, the old standard logic chips will not be produced any longer. Yes, you will be able to still find them, but there will not be any new ones produced. (Just my personal opinion).

Daryl

I think they will be around for a long time to come. The 74xx logic has been in use for some 40 years and it seems the sources keep expanding. Also, you may be thinking only in terms of computer usage. Yes, it is likely that 74xx hardware will gradually fade away in commercial computer usage (although not in hobby stuff like what we do). However, quite a bit of 74xx silicon is used a lot in non-computer applications. When I designed the control system for my 1.6 inch scale EMD F7 locomotive, I made use of some 74xx logic in it. It would have been that or scads of relays.

[8BIT]

Again, it is just my opinion. With the availability of all the microcontrollers and programmable logic, I see the commercial world moving away from the descrete logic chips. After that, manufactures will stop making them.

For our applications, placing the address decoding into programmable logic simplifies the board layout process because you can place less chips, have more flexibility in selcting which I/O pin connects to which device. You resolve all of the decoding in software and have much less propagation, increasing reliability and if desired, system clock speeds.

Daryl

[Bramblefax]

I'd like to play with some PALS/GALS, but I don't really know where to start. Does anyone know of some kind of "complete idiot's guide to programmable logic"?

[Bramblefax]

Also, a thought just occurred to me: is there anything stopping one from using a simple eprom/eeprom as an address decoder, aside from general wastefulness of a complex and useful chip on boring housekeeping functions? This would give us software-controlled glue logic without exotic software or hardware.

[faybs]

Horrendous propagation delays (they will be the access time of the ROM). An older EEPROM will have a propagation delay on the order of 200ns, while a newer flash will be around 70ns. PLDs have propagation delays that are around an order of magnitude smaller. Mind you, if that's not a problem (as Garth Wilson likes to say, at 1MHz you can get away with murder) it's a nice alternative.

[ElEctric_EyE]

Also, check out Fairchild's Tinylogic(tm) series of 3.3V discrete logic. Very low power and extremely fast speeds (1ns) approaching if not surpassing ECL bipolar tech.

Here's their OR gate: http://www.fairchildsemi.com/ds/NC/NC7SV32.pdf

It seems discrete logic is transforming into something awesome. For the hobbyist, forget about wirewrapping. DIP is soon to be gone. It seems like the circuit board houses have a unique opportunity to take advantage of these surface mount components, but I don't see them taking advantage of the newest surface mount spec's yet, which is disappointing. Maybe soon...

[8BIT]

Bramblefax wrote:

I'd like to play with some PALS/GALS, but I don't really know where to start. Does anyone know of some kind of "complete idiot's guide to programmable logic"?

This is what I did. it may not be the best way, but it got me from reading about it, to doing it.

Search for CPLD design documents from Atmel, Lattice, and Xilinx. They contain lots of info on logic blocks, and-or arrays, and other parts.

Download the datasheet for a PAL16V8. it will have some good info as well.

Next, download WINCUPL from Atmel
http://www.atmel.com/dyn/products/tools ... ol_id=2759

There are example files and in the help files is a CUPLREF.HLP that had info on the commands.

Start by building some simple logic equations for a GAL16V8.

You can play with the samples to make simple gates. It includes a simulator that lets you put wave forms on the inputs and test the outputs. Its kind of quirky, but it does work.

Once you have a few test projects completed, the next step is to buy a programmer. I found one on Ebay for around $50 6 yrs ago. You need to be sure they can program the 16V8 family.
Here's one: http://cgi.ebay.com/ws/eBayISAPI.dll?Vi ... 0414238812

With my programmer, I found it would program the ATMEL 16V8D, but not the ATMEL 16V8C.

Now, buy one or two 16V8's. You may want to get a small cross section from Atmel and lattice, and test if your programmer works with them.

Last, connect up your programmed device to a breadbaord and test it to see if the outputs are what you expect from the inputs given.

You can them go in to more complex logic and larger devices.

Hope this helps

Daryl

[GARTHWILSON]

I think the discrete logic ICs will be available for a long time, but certain older families will become available from fewer and fewer manufacturers, leaving more market share for the remaining ones, giving those more motivation to continue.

For hobbyists and prototyping, SOIC-to-DIP adapters are available, and I'm sure manual prototyping will continue almost indefinitely.

Yes at 1MHz you can get away with murder, but using an EPROM for address decoding would be mass murder; and even in our three-murder-deductible injustice system, you would not get away with that.