Hi everybody,
Long time no see. I've been very busy with schoolwork, and living in a country far away from any electronics stores and with an unreliable (as in usually 70% of packages are 'inspected') postage system, I had to put my electronics hobby on the side. However, over the past 2 weeks, I've had a lot of free time, so I finally got some of my act together, and have began designing an address decoder for my project. I have decided to have 4x32 kbyte SRAMs, an 8 kbyte 'bootloader' ROM, a 128 kbyte OS ROM, and a couple of I/O devices (such as an attiny for the keyboard and two VIA's). I have made a decoding circuit which involves 2 74138's, one 74139, and an an XNOR gate. Here is the schematic of the circuit as seen below (screenshot of a program):
Sorry for the confusing layout, but my scanner isn't working, and i was not able to scan the nice diagram I made... anyways, I've color coded the diodes, the green ones are the RAM, the red/purple ones the ROM, and yellow is the I/O devices. The gate with the '1' is a NOT gate, and the '=1' is a XOR gate.
Here is the address range i used in order to construct the circuit:
000000-007FFF RAM 1 (32 KB)
008000-00DFFF EMPTY (24 KB)
00E000-00FFFF boot ROM (8 KB)
010000-017FFF RAM 2 (32 KB)
018000-01FFFF RAM 3 (32 KB)
020000-027FFF RAM 4 (32 KB)
028000-037FFF Program slot 1 (64 KB)
038000-047FFF Program slot 2 (64 KB)
048000-067FFF O.S. ROM (128KB)
080000-0800FF VIA 1
080100-0801FF VIA 2
080200-0802FF AT Tiny (keyboard)
080300-0803FF AT Tiny (status lights on front panel)
080400-0804FF AT mega (video chip)
080500-0805FF AT mega (RS232 communications)
Unfortunately, I fear that since it is my first time designing such a thing, i have made the circuit too inefficient or have done something wrong with the way i designed it. I also am not sure how memory access works, the slowest chip i have has an access time of 120ns. I am wondering whether or not running at 4 Mhz will be appropriate, but I'm not sure how long it takes to read or write to memory, from what I understand, it allows a maximum (for 4 Mhz) 125 ns to do address decoding (and activate the chip), and another 125 ns to actually wait for the memory to spit out data.
Finally, if i use a latch, what latch should I use and how should I hook it up? I think that using the 74573 and hooking the pin to hold the output to phi2 is how i should do it, but i am not sure how to connect the data buses without causing interference to the address buses.