Adding SN76489 Sound Chip to Address Decoding?

[NickH93]

I've been building a 6502 machine and learning assembly, and at long last through trial and error, I've got my breadboard 6502 machine running! It just has a program for a simple LED blinking loop to test it, but it works. I have a WDC 65C02S, 65C51 ACIA, and 65C22 VIA. Haven't hooked up the ACIA as I'm waiting on the oscillator for it's baud rate generator to come in....

Anyway.

My address decoding all works, and I followed the first example of the 6502 Primer. Here's where I'm confused though:

The address decoding adds plenty of space for IO chips, and it expects a CS low and CS high signal to be properly selected on each chip

I want to add a Texas Instruments SN76489 chip. but it just has a CS low, and WE. WE gets hooked in with the WE (R/W) on the other chips, but then what goes to this only CE pin? Is it possible to add this chip with my current address decoding setup?

Thanks all!

[whartung]

Can't you just add an inverter to the CE signal for your chip?

[GARTHWILSON]

I started drawing a circuit with a pair of gates for the select; but I'm looking at the data sheet for it at ftp://ftp.whtech.com/datasheets%20and%2 ... N76489.pdf, and it looks like the write data must be valid and stable before the WR\ line goes down. Is that your understanding? The 65(c)02 does not do this, so you might need additional circuitry. The 65(c)02 will have the data ready no more than the specified setup time after Φ2 rises, but not before it rises; and Φ2 will be involved in producing the WR\ signal. Then I was looking for how long WR\ had to be down, and I'm seeing a requirement that you use RDY to stop the processor until the SN76489 says it's ok to continue. Do you have any idea how long it is? (It doesn't seem to be in the data sheet, although I did not take the time to comb through it meticulously.) It might almost be better to go through a VIA to interface to this part.

[NickH93]

GARTHWILSON wrote:

I started drawing a circuit with a pair of gates for the select; but I'm looking at the data sheet for it at ftp://ftp.whtech.com/datasheets%20and%2 ... N76489.pdf, and it looks like the write data must be valid and stable before the WR\ line goes down. Is that your understanding? The 65(c)02 does not do this, so you might need additional circuitry. The 65(c)02 will have the data ready no more than the specified setup time after Φ2 rises, but not before it rises; and Φ2 will be involved in producing the WR\ signal. Then I was looking for how long WR\ had to be down, and I'm seeing a requirement that you use RDY to stop the processor until the SN76489 says it's ok to continue. Do you have any idea how long it is? (It doesn't seem to be in the data sheet, although I did not take the time to comb through it meticulously.) It might almost be better to go through a VIA to interface to this part.

I appreciate the quick response. The only thing I could find is that it takes "around 32 clock cycles to load data into its control registers"

Come to think of it though, you're right. I'd probably have a much easier time doing this with the VIA chip. I have a spare IO port I'm not doing anything with.

I'll try that and see how it goes. Thanks for the help.

[GARTHWILSON]

NickH93 wrote:

The only thing I could find is that it takes "around 32 clock cycles to load data into its control registers"

I was hoping that that just meant that after writing to it, you had to give it time to digest the data while you go away and do other things before giving it more data, rather than that it would hold RDY low (false) for that long. Maybe that's not it though.

Quote:

Come to think of it though, you're right. I'd probably have a much easier time doing this with the VIA chip. I have a spare IO port I'm not doing anything with.

As I show in the 6502 primer, you can use the same VIA for a lot of things at once. Remember that besides the parallel ports, you can use CA2 and CB2 as general-purpose output bits, and CA1 and CB1 as interrupt-on-active-edge bits. (You select which edge you want in the PCR.) If you don't want it to actually generate an interrupt, you can leave the corresponding bits in the IER clear and just poll them in the IFR. You can select read latching of a VIA port in the ACR (although that's one of the few capabilities of the VIA that I have never used).

[cbmeeks]

The SN76489 was actually the first sound chip I got to work in my Arduino SoundBoard project. I later got both it and the AY-3-8912 to play VGM music with an Arduino.

Anyway, I do think you will have an easier time using the VIA for the SN76489. Also, I know it's not apples-to-apples, but I could dig up the Arduino code I did for accessing the SN76489 if you like. I remember it actually being much easier (timing wise) than the AY (but neither were difficult).

Keep us up to date on your progress!

[NickH93]

cbmeeks wrote:

The SN76489 was actually the first sound chip I got to work in my Arduino SoundBoard project. I later got both it and the AY-3-8912 to play VGM music with an Arduino.

Anyway, I do think you will have an easier time using the VIA for the SN76489. Also, I know it's not apples-to-apples, but I could dig up the Arduino code I did for accessing the SN76489 if you like. I remember it actually being much easier (timing wise) than the AY (but neither were difficult).

Keep us up to date on your progress!

That would help though, if you could. It'd be much appreciated! I've got my second VIA added and working with an LED, so now I have an IO port for it.

[NickH93]

Well, after scouring data sheets, I've successfully done it. The computer boots up, silence the chip and gives me a nice short beep. It is the same sound chip as the BBC micro, so the computer starting up sounds a lot like that.

So yes, my breadboard looks horrible. Never made one before. But here is where we stand now! https://scontent.cdninstagram.com/t50.2 ... 0560_n.mp4

[BigEd]

A most excellent startup sound!

[schlachet]

Tagging onto this thread in hopes of also getting the SN76489 working. I've got mine connected to a VIA, and while ignoring the ready pin, I've managed to get it muted, then produce a sound! Now that it's working, I wanted to try and do it the "right" way and read the ready pin. I've got it tied high with 2x1k ohm resistors in series. When I look at the pin with my LA, it looks like its just cycling continually, and it pauses when I have /WE high. I thought READY should remain low until the IC is doing something, and read high while its busy, then go low when it's ready to do something new. Am I missing something?

When I measure this pin on my scope, it reads as 62.50kHz

(D6 is /WE, D7 is READY)

[schlachet]

ok.. I have made some progress. I was treating /WE as active high, not active low. once I changed that, I got a different behavior from the ready pin. not working still, but think i'm on the right track. (and time to read the data sheet again)

[Dr Jefyll]

Glad to hear about the /WE progress.

schlachet wrote:

I thought READY should remain low until the IC is doing something, and read high while its busy

Better check, as that doesn't quite seem to add up. If READY behaves as you say then I'd expect the signal to be named /READY (or perhaps READY#), indicating active low. See what the data sheet has to say regarding this point.

-- Jeff

[BillO]

This is how I implemented it.

/QW is a Phi2 qualified write.

[BillO]

schlachet wrote:

ok.. I have made some progress. I was treating /WE as active high, not active low. once I changed that, I got a different behavior from the ready pin. not working still, but think i'm on the right track. (and time to read the data sheet again)

The READY signal goes low while the chip is loading in the data. The /CE and /WE pins need to be held low for that period of time too. That's why I used the READY pin to keep them low until it has loaded the data.

[GARTHWILSON]

Sometimes it gets viewed as RDY\ (ready-not), ie, active-low, but this is incorrect. RDY\ would imply that you put it low when you're ready to have the processor move on. It's not that way though. You put it low when you're not ready yet and need for it to wait. If the memory being accessed is always ready at the bus's clock speed, you keep RDY high to mean "I'm ready and I don't need any more time to get the data out." High means, "Yes! Ready! Go!" Low means, "No, I'm not ready! Don't go yet!" It is active-high.