NickH93 wrote:
The only thing I could find is that it takes "around 32 clock cycles to load data into its control registers"
I was hoping that that just meant that after writing to it, you had to give it time to digest the data while you go away and do other things before giving it more data, rather than that it would hold RDY low (false) for that long. Maybe that's not it though.
Quote:
Come to think of it though, you're right. I'd probably have a much easier time doing this with the VIA chip. I have a spare IO port I'm not doing anything with.
As I show in the 6502 primer, you can use the same VIA for a lot of things at once. Remember that besides the parallel ports, you can use CA2 and CB2 as general-purpose output bits, and CA1 and CB1 as interrupt-on-active-edge bits. (You select which edge you want in the PCR.) If you don't want it to actually generate an interrupt, you can leave the corresponding bits in the IER clear and just poll them in the IFR. You can select read latching of a VIA port in the ACR (although that's one of the few capabilities of the VIA that I have never used).