I took BDD's advice and changed the memory mapping a little. Here's the decoder circuit sheet.
Could you please post the new memory map? It may help with trying to figure out why you have enough gates in there to sink a small ship.
Also, I recommend you do not mix TTL logic with CMOS. 74HC devices will not see a valid logic 1 at their inputs if driven from TTL outputs. At best, the circuit will function, but likely be unstable. At worst, it won't work at all.
My hardware chops are a bit limited, but it looks to me like it's an output that's low for any bank 0 address in [$C000 .. $FFFF]. What the name means is something BDD should be able to answer.
Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!
I believe that's from his V2.0 design... it's Wait State Enable for anything in the I/O address block. Check out the full schematic under the Hardware Section:
When /WSE is asserted Ø2 is stopped (aka "stretched") in the high phase, resulting in a wait-state. Stretching avoids problems that may arise in trying to wait-state the 65C816 by controlling RDY. The clock generator circuit is in the below attachment.
Clock Generator w/Stretch Control
The generator circuit was derived from a prototype unit I built to prove the concept. The logic analyzer results for the prototype are below.
Clock-Stretching Logic Traces
Of the three clock outputs picked off at RN1, GCLK ("global clock") is not stretched and can be used to drive 65xx peripherals, such as the WDC 65C22. In particular, if the 65C22 is driven from Ø2, its timers will gradually slow down with each I/O or ROM access. Driving the 65C22 from GCLK avoids this problem. Implied in this case is that wait-stating would not be applied if the selected device is a 65C22. As I don't use the 65C22 I didn't include that "rule" in the glue logic. Such a rule might be awkward to implement in discrete logic, but wouldn't be a problem with a PLD.
Jumper JP1 on the left selects one or two wait-states. I added that feature to POC V2.0's clock generator for experimentation purposes.
floobydust wrote:
I believe that's from his V2.0 design...
...also used in V1.3.
barrym95838 wrote:
My hardware chops are a bit limited, but it looks to me like it's an output that's low for any bank 0 address in [$C000 .. $FFFF].
So it's probably not going to be relevant to my design?
That's something you will have to decide. The need for wait-stating will depend on how fast you want to run your system and the performance of the parts you use to build it.
This is kind of a test bed for me right now so I'm thinking no more than 4 MHz.
Unless you use some really slow stuff you won't need wait-states at 4 MHz. Just remember what I earlier said about mixing TTL and CMOS logic. There is no valid reason at this time to use TTL logic in a new design.
I am a little bit angry right now. It seems like there are no DIP EPROM or EEPROMs that work on 3.3V, meaning I might have to jack up the main rail to 5V or add a PLCC32 socket for one of Atmel's 3.3V offerings (the OTP EPROM and the EEPROM are not pin compatible in PLCC32).
I just did a brief search and found the 28LV010 which appears to have a DIP version ... is this not available or not applicable for some reason?
[Edit: might be for aerospace use, so rare and expensive?]
Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!
