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Got two 65816 instead of 6502 by mistake: advice needed.

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tokafondo

Post subject: Got two 65816 instead of 6502 by mistake: advice needed.

Posted: Tue May 25, 2021 12:16 pm

Joined: Sat Apr 11, 2020 7:28 pm
Posts: 344

I ordered two 6502 chips from Europe's WDC partner and received two 65816 chips.

So much has been told about the 816's advantages when programming.

But hardware wise, maybe it's not the same. And I'm talking about use them in emulation mode all the time.

Is there something, and again hardware wise, that a real 6502 would be able to do that a emulated 6502 wouldn't, that would require to have the former instead of his big brother?

Or can I just use a 6502 design and put a 65816 instead, while observing the pins differences?

They have replaced 6502s with 65816 in several classic computers and with the appropiate adaptations, they seemed to continue working fine...

Thanks, all.

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drogon

Post subject: Re: Got two 65816 instead of 6502 by mistake: advice needed.

Posted: Tue May 25, 2021 12:51 pm

Joined: Wed Feb 14, 2018 2:33 pm
Posts: 1488
Location: Scotland

tokafondo wrote:

The software differences are the bit operations - SBR/BBR. These are 65C02 only. That initially bit me until I switched the assembler into '816 mode then they were flagged, but if your code is non-"C" 6502 code, then you won't have them anyway.

Other than that, in emulation mode (default at power on) I don't think you'll notice. Also, hardware wise - while there may be a potential issue on my simple little board at 16Mhz I didn't see any issues but the only peripheral I had on that one was a VIA and GAL to do the decoding, etc. when I moved it from a W65C02 to W65C816 I just pulled pin 3 high via 3.3K resistor and stuck an LED on the Emulation output pin.

https://projects.drogon.net/ruby-6502-b ... uby-65816/

There are extra hardware vectors you'll need if you go into native 816 mode - mainly BRK which now has one of its own, but in emulation mode it's all the same.

There is also a potential issue during clock low as the data bus is driven with the upper 8-bits of the address bus - others may go into more detail but it's not affected my simple little system so-far.

-Gordon

_________________
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Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

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tokafondo

Post subject: Re: Got two 65816 instead of 6502 by mistake: advice needed.

Posted: Tue May 25, 2021 4:37 pm

Joined: Sat Apr 11, 2020 7:28 pm
Posts: 344

I'm seeing also that the 6502 can drive an external oscillator or resonator, but the 65816 needs the clock generated outside and fed with it.

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drogon

Post subject: Re: Got two 65816 instead of 6502 by mistake: advice needed.

Posted: Tue May 25, 2021 5:29 pm

Joined: Wed Feb 14, 2018 2:33 pm
Posts: 1488
Location: Scotland

tokafondo wrote:

I'm seeing also that the 6502 can drive an external oscillator or resonator, but the 65816 needs the clock generated outside and fed with it.

Hm. Yes. That never occurred to me as I've always used an external can osc., but yes, so if a new design, use a can maybe...

-Gordon

_________________
--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

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BigDumbDinosaur

Post subject: Re: Got two 65816 instead of 6502 by mistake: advice needed.

Posted: Thu May 27, 2021 4:15 am

Joined: Thu May 28, 2009 9:46 pm
Posts: 8505
Location: Midwestern USA

tokafondo wrote:

I'm seeing also that the 6502 can drive an external oscillator or resonator, but the 65816 needs the clock generated outside and fed with it.

HCMOS clock oscillators are cheap and reliable, so the 65C816's clock requirements are not a problem to meet. If you don't plan to run the machine very fast you can hook the oscillator's output directly to the 816—no muss, no fuss. Note that the oscillator must generate CMOS output levels and for most reliable performance, should have an output rise/fall time at or below 5ns. Most any good-quality oscillator will meet those specs.

Once the Ø2 speed goes into double digits it is best to have the oscillator drive a C-D flip-flop (e.g., 74AC74) to assure a 50-50 output duty cycle and avoid possible timing issues that an asymmetric clock can bring. Another technique, useful for a 65C816 unit that will not being using extended RAM, but needing wait-stating, is to use Jeff's wait-state clock generation scheme, which is a single-chip solution that addresses the symmetry issue, as well as wait-stating via clock stretching. If you go that route, I recommend the use of a 74AC163 to achieve the fast edges required by the 816. I have tested Jeff's circuit in POC V1.2 at 20 MHz—it works like charm.

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x86? We ain't got no x86. We don't NEED no stinking x86!

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BigDumbDinosaur

Post subject: Re: Got two 65816 instead of 6502 by mistake: advice needed.

Posted: Thu May 27, 2021 4:36 am

Joined: Thu May 28, 2009 9:46 pm
Posts: 8505
Location: Midwestern USA

drogon wrote:

Also, hardware wise - while there may be a potential issue on my simple little board at 16Mhz I didn't see any issues but the only peripheral I had on that one was a VIA and GAL to do the decoding...There is also a potential issue during clock low as the data bus is driven with the upper 8-bits of the address bus - others may go into more detail but it's not affected my simple little system so-far.

The 65C22 "understands" the 6502-type bus cycle and thus it is remarkably easy to interface to the 65C816. The C22 will not drive the data bus during a read cycle until Ø2 goes high, so the potential for contention right at the clock's rising edge is theoretically non-existent. If there is any concern about that, a data bus transceiver can be used to isolate the C22 from the MPU whilst Ø2 is low.

In the case of using non-65xx silicon, there can definitely be a problem during a read cycle if an addressed device gets on the data bus too soon—severe contention will result and if the A16-A23 bits are being used to control extended RAM, a major mess may occur. Qualifying /RD with Ø2 will handle that issue. Similarly, qualifying /WD with Ø2 will prevent wild writes as the 816 sets up the address bus during Ø2 low. Neither technique is required with 65xx devices and in fact, must not be used with such devices.

Lastly, the address bus behavior of the 65C816 is that of the NMOS 6502, not the 65C02, even in emulation mode. Invalid addresses may be formed during some stages of instruction execution, which can give you some grief, especially with I/O hardware. The VDA and VPA signals are present to indicate when the address bus is not emitting a valid address. Their use in qualifying I/O device selection will prevent hard-to-diagnose hardware bugs.

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x86? We ain't got no x86. We don't NEED no stinking x86!

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tokafondo

Post subject: Re: Got two 65816 instead of 6502 by mistake: advice needed.

Posted: Sat May 29, 2021 3:05 pm

Joined: Sat Apr 11, 2020 7:28 pm
Posts: 344

Well I tested the 74HC14 clock circuit, with a capacitor in series with the input and a resistor in the input in parallel with the output as shown in the left, ticking more or less at the amazing speed of ~1 (one) hertz. I put some LEDs in the address lines, Ben Eater's stytle, to be sure the CPU was doing something.

Attachment:

IMG_20210529_155708_568.jpg [ 163.95 KiB | Viewed 1110 times ]

And the '816 will take it. It's of course a non reliable method to get the CPU kicking at higher speeds.

In the center there is a ceramic resonator I pulled out from a Denon music amplifier, that used a MCU to manage the sound inputs and outputs. It runs at 4 mhz and of course will also make the '816 run.

Well... let's see what I can do from here...

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BigDumbDinosaur

Post subject: Re: Got two 65816 instead of 6502 by mistake: advice needed.

Posted: Sat May 29, 2021 4:33 pm

Joined: Thu May 28, 2009 9:46 pm
Posts: 8505
Location: Midwestern USA

tokafondo wrote:

Why, at the blazing speed of 1 Hz, POC V1.3 should be able to complete all three POST stages in about 22 hours.

Quote:

The 816 has a fully static code, hence the lowest clock rate at which it can maintain state is 0 Hz.

BTW, for a real-world application, use of a CMOS can oscillator is the preferred clock source. WDC specs say the rise/fall time of the Ø2 signal should not exceed 5ns. Once Ø2 gets into double-digits, it's a good idea to run the oscillator through a flip-flop (74AC74 or 74AHC74 recommended) to ensure clock symmetry and avoid potential timing gotchas. The 74A(H)C74 can be used in conjunction with a 74AC109 to create a clock source that can be stretched to accommodate slow hardware—the illustrated method would be used if extended RAM is present. A simpler, one-chip solution, suitable for an 816 system without extended RAM, or a 65C02 system, is documented here

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