A multiprocessor system with mainly just the 6502 (?)

[Aloha6502]

BigEd wrote:

Hmm. I've just had a thought. Because the 6502 (and 6800 and 6809, perhaps) only needs active use of the bus for one half of the cycle, it's a common idea, often enough implemented, to have two CPUs sharing the same memory bus. So far so good.

So, if we had a chain of CPUs, each separated by a shared memory, the same odd/even timing could be used. The CPUs at the ends of the chain have only one memory, but it's still shared by the adjacent one. All the others have two memories, one to the left and the other to the right. Any mailboxes or semaphores or data buffers would of course be in the appropriate shared memory depending on which direction the relevant resource is to be found.

Sorry, I am not following too well here.

So, when you mention half cycle, do you mean taking the clock signal and inverting it for one CPU, so they are basically out of phase? (But some instructions take more than one cycle to complete, right?)

For the daisy chained CPUs, I am not too clear on the memory sharing you mention.

[BigDumbDinosaur]

Aloha6502 wrote:

BigDumbDinosaur wrote:

What you are referring to is "ROM shadowing," a technique that goes back to the 1970s...

Is this what all the "Zero Wait State" marketing was about in the 1980s?

Yessir. It was a really big deal in those days, even when the 8088 was running at a screaming 4.77 MHz. Nowadays, PeeCees still do wait-stating but no one outside of the engineers who designed the motherboard pays any attention to it—wait-states are just another feature of the hardware on the same level of importance as the color of the PCB. Also, the option to disable ROM shadowing has long disappeared from the setup functions.

[Aloha6502]

BigDumbDinosaur wrote:

Aloha6502 wrote:

BigDumbDinosaur wrote:

What you are referring to is "ROM shadowing," a technique that goes back to the 1970s...

Is this what all the "Zero Wait State" marketing was about in the 1980s?

Yessir. It was a really big deal in those days, even when the 8088 was running at a screaming 4.77 MHz. Nowadays, PeeCees still do wait-stating but no one outside of the engineers who designed the motherboard pays any attention to it—wait-states are just another feature of the hardware on the same level of importance as the color of the PCB. Also, the option to disable ROM shadowing has long disappeared from the setup functions.

For the 6502, to achieve these useless pauses should it just be as simple inserting a series of NOPs ($EA) between each actual instruction? Say, for the ROM shadowing upon boot up, copying each memory location from ROM, using indexing, but adding NOPs in the loop, before JMP to the RAM-only operating system thereafter?

[BigEd]

> So, when you mention half cycle, do you mean taking the clock signal and inverting it for one CPU, so they are basically out of phase?

Yes, that's the plan: one CPU's phase one is another CPU's phase two.

> (But some instructions take more than one cycle to complete, right?)

Indeed, but that doesn't matter. It's not that the CPUs are running alternate instructions, they are using the same memory on alternate phases.

[GARTHWILSON]

Aloha6502 wrote:

For the 6502, to achieve these useless pauses should it just be as simple inserting a series of NOPs ($EA) between each actual instruction? Say, for the ROM shadowing upon boot up, copying each memory location from ROM, using indexing, but adding NOPs in the loop, before JMP to the RAM-only operating system thereafter?

Wait states are for each individual memory (or I/O) access, of which there is usually more than one in a single instruction. Just putting more time between instructions won't help. Jeff has some good explanations and diagrams, like in his post at viewtopic.php?p=66907#p66907 .

[Aloha6502]

BigEd wrote:

> So, when you mention half cycle, do you mean taking the clock signal and inverting it for one CPU, so they are basically out of phase?

Yes, that's the plan: one CPU's phase one is another CPU's phase two.

> (But some instructions take more than one cycle to complete, right?)

Indeed, but that doesn't matter. It's not that the CPUs are running alternate instructions, they are using the same memory on alternate phases.

That's what I mean. If the instructions take more than one cycle, wouldn't there possibly be overlapping contention on the bus to access the same memory at the same time?

[BigEd]

Hmm. You and I seem to have different mental models. I'm pretty sure of mine. I'm afraid I don't understand yours well enough to try to explain the difference. There's something going on in your model which sees multi-cycle instructions as special. (In fact, all instructions are multi-cycle, so that's another mystery to me!)

Have you a picture of what happens in each cycle of a simple or of a complex instruction? There are documents which tabulate that, and there's visual6502 for a live demo in your browser.

[drogon]

Aloha6502 wrote:

BigEd wrote:

> So, when you mention half cycle, do you mean taking the clock signal and inverting it for one CPU, so they are basically out of phase?

Yes, that's the plan: one CPU's phase one is another CPU's phase two.

> (But some instructions take more than one cycle to complete, right?)

Indeed, but that doesn't matter. It's not that the CPUs are running alternate instructions, they are using the same memory on alternate phases.

That's what I mean. If the instructions take more than one cycle, wouldn't there possibly be overlapping contention on the bus to access the same memory at the same time?

The simple answer is no.

The 6502 only accesses memory, peripherals, etc. every half cycle. That's how its designed. So if you have 2 of them on the same memory system and arrange them to use alternate half cycles then it will work.

This is how video was done back in the day. the 6502 would see the RAM and the video engine would also see the same RAM but on alternate half cycles. If done correctly then both the 6502 and video would run without any interference and at full speed.

-Gordon

[Aloha6502]

BigEd wrote:

Hmm. You and I seem to have different mental models. I'm pretty sure of mine. I'm afraid I don't understand yours well enough to try to explain the difference. There's something going on in your model which sees multi-cycle instructions as special. (In fact, all instructions are multi-cycle, so that's another mystery to me!)

Have you a picture of what happens in each cycle of a simple or of a complex instruction? There are documents which tabulate that, and there's visual6502 for a live demo in your browser.

No that's what I mean. I understand that bit. I guess if we were to narrow it down, what I might not be understanding, or I am assuming, is that when you say the CPUs are driven by out of phase clock cycles, and the instructions are multi cycle, then how does the out of phase clock signal do anything to separate the CPUs from clashing on accessing the same memory chips, on the same bus? If the memories and bus are totally separate then why bother to put one CPU out of phase? I think this is the part that I am not understanding.

[Aloha6502]

drogon wrote:

Aloha6502 wrote:

BigEd wrote:

> So, when you mention half cycle, do you mean taking the clock signal and inverting it for one CPU, so they are basically out of phase?

Yes, that's the plan: one CPU's phase one is another CPU's phase two.

> (But some instructions take more than one cycle to complete, right?)

Indeed, but that doesn't matter. It's not that the CPUs are running alternate instructions, they are using the same memory on alternate phases.

That's what I mean. If the instructions take more than one cycle, wouldn't there possibly be overlapping contention on the bus to access the same memory at the same time?

The simple answer is no.

The 6502 only accesses memory, peripherals, etc. every half cycle. That's how its designed. So if you have 2 of them on the same memory system and arrange them to use alternate half cycles then it will work.

This is how video was done back in the day. the 6502 would see the RAM and the video engine would also see the same RAM but on alternate half cycles. If done correctly then both the 6502 and video would run without any interference and at full speed.

-Gordon

OK you may have answered the question I had for BigEd.

So if I am understanding, the 6502 will ONLY access the bus either on a HIGH or a LOW clock signal (I assume HIGH?). So there is no way for the other CPU to access the bus if it is directly out of phase.

But does this mean the bus electrical signals will FOR SURE not still be in a kind of residual voltage level when the next CPU does something on it?

[BigEd]

(crossed in the post)

They don't clash because they are operating on opposite phases.

I think it goes like this:

In a second, a 6502 running at 1MHz makes a million memory accesses. Another 6502 running on the opposite phase also makes a million memory accesses. The memory itself sees two million accesses.

In any given phase, only one thing drives the data bus: one or other of the CPUs, if a write, or the memory, if it's a read. One or other of the CPUs drives the address bus.

[Aloha6502]

BigEd wrote:

(crossed in the post)

They don't clash because they are operating on opposite phases.

I think it goes like this:

In a second, a 6502 running at 1MHz makes a million memory accesses. Another 6502 running on the opposite phase also makes a million memory accesses. The memory itself sees two million accesses.

In any given phase, only one thing drives the data bus: one or other of the CPUs, if a write, or the memory, if it's a read. One or other of the CPUs drives the address bus.

OK many thanks. Now it is much clearer to me.

[Aloha6502]

So, even at 25 MHz, that is still slow enough that we can ignore any concerns about residual voltages on the bus?

[BigEd]

It's the nature of driving a bus that it starts at one voltage and ends up at another. The question then is whether the bus is fast enough: driven early enough, and hard enough, and sensed reliably enough, to work at some speed.

It's the nature of this idea of using both phases of the clock that the memory system needs to be able to run at double the speed of the CPU clock.

It's not trivial to get a system to work fast, in any case, and this approach isn't going to make it easier.

Personally I haven't seen a 6502 family system run any faster than 16MHz (and possibly not even that) but it's all a matter of degree: how fast are the parts, how clean is the implementation.

[GARTHWILSON]

Aloha6502 wrote:

So, even at 25 MHz, that is still slow enough that we can ignore any concerns about residual voltages on the bus?

Reinforcing what Ed said, "residual" implies voltages held by the bus capacitance when nothing is driving the bus.  With only CMOS loads, the capacitance can hold the value for not just nanoseconds, and not just microseconds, but even milliseconds; but ideally the design has one driver shut off before the next driver becomes active, with the smallest amount of delay that won't produce contention.  I've never heard of any 65xx computers doing the two processors on the same bus out of phase at more than a MHz or two though, let alone three or more processors.  I'm sure that if you want the higher clock rates and want to keep the processors active all the time, you'll need either dual-port RAMs or have the various computers more loosely coupled through their I/O rather than sharing buses.  The I/O coupling does not need to be much of a bottleneck if the jobs doled out are relatively large compared to the size of the instruction and accompanying data, like for example drawing an arc on the display with a certain center point and perhaps the beginning and ending angles, letting the slave figure out all the pixels and feed them to the LCD.