Hmm. I've just had a thought. Because the 6502 (and 6800 and 6809, perhaps) only needs active use of the bus for one half of the cycle, it's a common idea, often enough implemented, to have two CPUs sharing the same memory bus. So far so good.

So, if we had a chain of CPUs, each separated by a shared memory, the same odd/even timing could be used. The CPUs at the ends of the chain have only one memory, but it's still shared by the adjacent one. All the others have two memories, one to the left and the other to the right. Any mailboxes or semaphores or data buffers would of course be in the appropriate shared memory depending on which direction the relevant resource is to be found.

For the 6502, to achieve these useless pauses should it just be as simple inserting a series of NOPs ($EA) between each actual instruction? Say, for the ROM shadowing upon boot up, copying each memory location from ROM, using indexing, but adding NOPs in the loop, before JMP to the RAM-only operating system thereafter?

> So, when you mention half cycle, do you mean taking the clock signal and inverting it for one CPU, so they are basically out of phase?

Yes, that's the plan: one CPU's phase one is another CPU's phase two.

> (But some instructions take more than one cycle to complete, right?)

Indeed, but that doesn't matter. It's not that the CPUs are running alternate instructions, they are using the same memory on alternate phases.

That's what I mean. If the instructions take more than one cycle, wouldn't there possibly be overlapping contention on the bus to access the same memory at the same time?

Hmm. You and I seem to have different mental models. I'm pretty sure of mine. I'm afraid I don't understand yours well enough to try to explain the difference. There's something going on in your model which sees multi-cycle instructions as special. (In fact, all instructions are multi-cycle, so that's another mystery to me!)

Have you a picture of what happens in each cycle of a simple or of a complex instruction? There are documents which tabulate that, and there's visual6502 for a live demo in your browser.

The simple answer is no.

The 6502 only accesses memory, peripherals, etc. every half cycle. That's how its designed. So if you have 2 of them on the same memory system and arrange them to use alternate half cycles then it will work.

This is how video was done back in the day. the 6502 would see the RAM and the video engine would also see the same RAM but on alternate half cycles. If done correctly then both the 6502 and video would run without any interference and at full speed.

-Gordon

(crossed in the post)

They don't clash because they are operating on opposite phases.

I think it goes like this:

In a second, a 6502 running at 1MHz makes a million memory accesses. Another 6502 running on the opposite phase also makes a million memory accesses. The memory itself sees two million accesses.

In any given phase, only one thing drives the data bus: one or other of the CPUs, if a write, or the memory, if it's a read. One or other of the CPUs drives the address bus.

So, even at 25 MHz, that is still slow enough that we can ignore any concerns about residual voltages on the bus?