POC Computer Version One

[floobydust]

That is an odd problem, but I've had similar things occur over the years... even recently with my latest creation of a Compact Flash interface. My intermittent issue turned out to be supply voltage. I have multiple 5V@3A switching/regulated supplies... turns out voltage sensitivity was the problem. I ended up with a supply that was a bit over 5.1V and that worked better on a test setup... dropping the voltage down to 5.0V had some intermittent failures.

Based on what you found, I would suspect RAM first... and possibly one of the DUARTs as a possible second, unless you can verify that the buffer and SIO output are always a match. Other than these... there could be some odd noise somewhere. Do post an update on what you find.

[BigDumbDinosaur]

BigDumbDinosaur wrote:

Flaky MPU. Again, pretty rare—I've never encountered a bad MPU in some 50-odd years of monkeying with computer hardware. However, there's always a first time for everything. I should be able to eliminate this possibility by swapping MPUs with POC V1.1, which completes the test code without error, thus implying it has a good MPU.

Scratch that possibility. I put V1.2's MPU into V1.1 and re-ran the test. It completed without error.

I'm suspecting a flaky RAM. I'm going to write a detailed RAM test to see if I provoke the problem, as it is intermittent.

BTW, an interesting thing came up when I tried to run V1.2 with V1.1's MPU. It wouldn't boot, even with Ø2 at 4 MHz. V1.1's MPU is an old part with a Sanyo 0.8µ core. It will run at 14.1 MHz in POC V1.1. So that turn of events has me puzzled—solving it is something for another time.

[BigDumbDinosaur]

floobydust wrote:

My intermittent issue turned out to be supply voltage. I have multiple 5V@3A switching/regulated supplies... turns out voltage sensitivity was the problem.

I use an old ATX power supply as my power source. According to my DVM, the five volt output is 5.08.

See my previous post for my suspicions.

[enso]

More likely a power distribution problem, possibly decoupling... Can you scope a few places, preferrably recording a lot of samples?

A noisy circuit that just barely works at 5.1V can stop working at 5.0V if the noise pokes through the floor... I think there is a bad spike when compact flash turns on (I seem to remember having to decouple a lot; one of my CF interfaces just never worked)...

[BigDumbDinosaur]

enso wrote:

More likely a power distribution problem, possibly decoupling... Can you scope a few places, preferrably recording a lot of samples?

It's a four-layer board with inner ground and power planes. Every piece of silicon has a decoupling capacitor (0.1 µF), plus there are several low-ESR electrolytics on the board, including one right at the power input jack.

My voltage checks were made at the power input jack and at each device. Furthermore, I have scoped Vcc while the unit is running and have seen nothing in the way of noise. I do not suspect power problems at this time.

Quote:

A noisy circuit that just barely works at 5.1V can stop working at 5.0V if the noise pokes through the floor... I think there is a bad spike when compact flash turns on (I seem to remember having to decouple a lot; one of my CF interfaces just never worked)...

All high-speed (meaning high switching speed, not high clock speed) circuits will exhibit some ringing, especially on a PCB that doesn't have controlled impedance. However, as long as ringing dies out before a device's timing is violated it should not be a problem. Incidentally, a sample scoping of some of V1.2's circuits shows less ringing than I've seen on V1.1, which machine is very stable at 14 MHz. Like V1.2, V1.1 uses 74AC logic, which is notorious for its extremely fast switching times.

I am contemplating the replacement of the SRAM, as it seems at this point to be the likely source of the problem. Trouble is it's an SMT device and while I can desolder the old one without wrecking the PCB, soldering in a new one is going to be a major challenge. However, before doing any hardware butchery I am going to write a detailed RAM test program to see if I can narrow down the address range in which the apparent corruption is occurring. The problem comes and goes, which of course makes troubleshooting a challenge.

[GARTHWILSON]

I kind of expect it will turn out to be something simple that nobody here (including myself) has thought of.

[BigDumbDinosaur]

GARTHWILSON wrote:

I kind of expect it will turn out to be something simple that nobody here (including myself) has thought of.

Maybe, although the problem seems to come and go. One thing I did notice was that when the error occurred the addresses at which the erroneous data was being "read" were always close to each other. That's part of the reason why I'm increasingly thinking the SRAM is the culprit.

[floobydust]

Well, you gotta hate having to remove SMT devices.... if you can get a fine detailed view of the solder connections, perhaps one of the connections have become a bit flaky. Perhaps touching up the joints first, or try adding an extra decoupling cap directly on the Vcc and Gnd pins.

Other than that, getting a good memory test running can't hurt. The old "6502 Assembly Language Subroutines" book has a decent memory test which might be useful. It does the usual fill bytes of $00, $FF, $55, $AA and a walking bit test from high bit to low bit. You could add to this test by inverting the walking bit test passing a "0" bit (all others at "1") through as well.

It will be interesting to see what the cause is...

[floobydust]

enso wrote:

More likely a power distribution problem, possibly decoupling... Can you scope a few places, preferrably recording a lot of samples?

A noisy circuit that just barely works at 5.1V can stop working at 5.0V if the noise pokes through the floor... I think there is a bad spike when compact flash turns on (I seem to remember having to decouple a lot; one of my CF interfaces just never worked)...

I recently designed an adapter for my C02 Pocket SBC, which provides 16-bit access for Compact Flash and a DS1511Y RTC. Certain CF cards were (and still are) problematic... so I finally limited my interface for using authentic SanDisk cards (Note: there are a lot of remarked CF Cards which aren't true SanDisk). I also redesigned the PCB and added additional decoupling and filtering for the CF Card. Since then, it's been flawless (have 3 systems operating now) running my own test programs and using the newer ROM version of DOS/65 (supports CP/M disk formats). I still need to clean up some test code for the CF Card interface, but the last BIOS update appears to be very solid. I would also note that Bill (Plasmo here) found similar problems much earlier than I did and also came up with some clever ideas to help resolve the problems.

Back to regular programming now....

[enso]

BDD, what is the stackup in your 4 layers?

I used to think that just having 4 layers with a ground plane is guaranteed success. I recently found out why a couple of my 4-layer boards were much noisier than I expected: I had signal-ground-power-signal stackup, which is a big problem as the bottom layer does not have access to the ground plane, and power distribution suffered as the ground plane was too far away across the core. Any boards I make from now on will have two ground planes, no power plane.

I am sure you'd notice a voltage dip from CF. I would still try a bigger cap (maybe 10) near the CF, as it is a 'light-dimming' device when it kicks in. It will cause a voltage drop, and some IC in the critical timing path may become a tiny bit slower...

I may be barking up the wrong tree and don't mean to step on your toes - you know a lot more about your system. Just an extra pair of eyes.

[enso]

BDD, I misread the CF comment as yours.

[BigDumbDinosaur]

enso wrote:

BDD, what is the stackup in your 4 layers?

The bottom inner layer is Vcc, top inner is ground. The boards for all three versions of the POC V1 series are the same makeup.

Quote:

I used to think that just having 4 layers with a ground plane is guaranteed success. I recently found out why a couple of my 4-layer boards were much noisier than I expected: I had signal-ground-power-signal stackup, which is a big problem as the bottom layer does not have access to the ground plane, and power distribution suffered as the ground plane was too far away across the core.

The Vcc layer will look like a ground plane to the bottom layer if there is sufficient bypassing. All my POC units have the DC power input bypassed with a 0.1µF MLCC and a low-ESR electrolytic in parallel. Each piece of silicon is bypassed by a 0.1 µF MLCC and at the expansion socket, the MLCC is again paralleled with a low-ESR electrolytic. The MLCC/electolytic parallel combination is also present at each of the MAX238s that drive the serial ports. From an AC perspective, both inner layers look like ground.

Quote:

Any boards I make from now on will have two ground planes, no power plane.

As long as you can find room to route Vcc in a way that will avoid any voltage loss...

[BigDumbDinosaur]

floobydust wrote:

Well, you gotta hate having to remove SMT devices.... if you can get a fine detailed view of the solder connections, perhaps one of the connections have become a bit flaky. Perhaps touching up the joints first, or try adding an extra decoupling cap directly on the Vcc and Gnd pins.

Touching up the SRAM's connections is going to be a challenge. I have no central vision in one eye, and of course, no depth perception for working close up.

Quote:

Other than that, getting a good memory test running can't hurt.

The memory test is running as I speak, so to speak. As the problem seems to come and go, it may be a while before a failure occurs.

[GARTHWILSON]

Ideally there would be a bypass capacitor from the power plane to the ground plane next to every place a signal trace goes through a via to the other side of the board, so the return can run next to it. Then the ground-plane access won't be a problem. Dr. Johnson even tells how to keep the characteristic impedance constant through that transition, although we don't need to go to that extent in the stuff we're working on here. It will never be perfect; but we can get plenty close for our uses.

[BigDumbDinosaur]

GARTHWILSON wrote:

Ideally there would be a bypass capacitor from the power plane to the ground plane next to every place a signal trace goes through a via to the other side of the board, so the return can run next to it.

That's not particularly practical on dense PCBs. Just looking at POC V1.2's board, I can see multiple locations where via are too closely packed to even get the smallest chip capacitors in there. Also, if bypassing were to be implemented anywhere a signal changes sides you might find yourself placing a cap at many of the pins on each device. The capacitor manufacturers would be delighted, the guy or gal assembling the board would be cursing.

Quote:

...although we don't need to go to that extent in the stuff we're working on here.

Ain't that fortunate?