BigDumbDinosaur wrote:
maewn21 wrote:
Long story short replacing the 74HCT04 with a much slower but pin compatible CD40106 solved the problem and everything works just fine.
My theory here is that with the 74HCT04 \WR was probably pulled down way before the address I wanted to write to was stable.
Your theory may be correct and if so, is telling you your glue logic design is incorrect. 
If you are using Ø2 to qualify chip selects, the UART will not have been selected at the time /WD (write data) goes low, this being due to the time required for the UART to respond to /CS (chip select) being asserted. This being the case. it's likely an internal violation of the UART's timing has occurred, resulting in a wrong register being briefly "touched."
Succinctly stated, the device—UART in this case—should be selected without reference to the state of Ø2. The 65C02 generates a valid address midway through Ø2 low. Glue logic should take advantage of that to maximize timing headroom. As a fairly general rule, the device's /CS should be asserted before /RD (read data) or /WD is asserted. Aside from guaranteeing the correct register has been selected before a read or write operation, following this rule may improve device performance in some cases, as many devices' response to /CS is slower than to /RD or /WD. In the case of E(E)PROMs, this difference may be considerable.
Note that the 65xx-compatible I/O devices—65C22, 65C51, etc.—must not have any aspect of their operation qualified by Ø2. As those devices have a dedicated Ø2 input, they will "know" about the 65C02 bus cycle and will not sample RWB until Ø2 goes high.Yes I did notice that 65xx-compatible I/O devices have a Ø2 input and don't need the kind of glue logic I'm using as I was looking on PET and C64 schematics to see how they do the \RD \WR logic. (which was somewhat disappointing since they don't have this kind of logic)
My \CS signals are not qualified by Ø2 as you can see in the schematic I've posted when I started this thread. The only things that I qualify by Ø2 are \RD \WR. Still looking at the timing diagrams in the 6502 datasheet I figured that Ø2 goes high long before anything on the data bus is valid and if I understand that right, this should'nt matter when reading from ROM but may write whatever is on the data bus into the RAM if it's fast enough. 15ns RAM in my case. (I may have actually mixed up data bus and address bus when posting my update, I didn't have the datasheet open at this time. Sorry for that)
I'm using an NMOS 6502 (just guess it's NMOS. it draws ~100mA, gets quite warm, it's sanded off and relabeled). Not sure if that makes any difference with the timing compared to the CMOS version.
About the UART, after fixing that timing problem I tried the UART chips that I declared dead and they still only send out gibberish. So them not working wasn't caused by the timing issue.
Anyways it's working now and I have adapted the Intel hex loader from the code section of the site to work with the 16550. So I can finally just copy paste hex files into putty instead of swapping the ROM all the time. I do however think about putting some jumpers on the now grounded and unused address lines of the ROM so I could easily switch between a few programs besides the hex loader. Some version of Basic comes to mind and maybe something to dump the RAM contents thru the serial port.
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