cjs wrote:
So, beyond doing 80 columns, it seems to have 512 KB of memory, built-in bank switching, and not least a 65816 CPU running at that higher speed! Certainly an interesting project. And I also agree with you that the MiniPET's use of an Atmel MCU to emulate the original PET's video system feels like a bit of a cheat, and the CPLD less so. (Also, the MiniPET's dual-ported RAM is moderately expensive and rare.) Though I'd still like to see it done one day without even the CPLD.
The problem of doing this without a CPLD (or some other higher-integrated video / glue logic chip) is, that you'll end up with a PET board basically (maybe optimized but still).
Admittedly, if you optimize to a SRAM, and a large ROM, use BE instead of separate drivers lots of the glue gets optimized away, but still...
I'm targeting 8MHz CPU speed outside the visible screen area, but not all of this memory bandwidth is available during screen fetches. In 80col charrom mode it will be reduced to 4MHz during the screen fetch (2 MHz character fetch, 2 MHz char"rom" fetch from RAM, rest 4MHz for CPU)
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However, I wonder about the name. Your system seems to be not smaller than but considerably larger than the MiniPET in terms of capabilities, and I'm guessing the BOM cost is also going to be more expensive, or at least around the same price. (Correct me if I'm wrong about that.)
Thanks, yes I was actually wondering why the MiniPET was so restricted in capabilities - one trigger to work on that project.
About the BOM - I am not sure what is more expensive. The CPLD is basically 40€ - and the rest should be on the MiniPET just as well - the CPU, VIA, PIAs, I/O buffers, Voltage control.
My current version is still using the mc3446 which are prohibitively expensive, but I'll plan to use 74ls640-1 that can drive IEEE488 compatible currents and are still available.
Also, my board is - if I judge the pictures correctly - quite a bit smaller than the MiniPET (thus also the name).
The I/O part is basically 1:1 copy of this board
http://www.6502.org/users/andre/csa/petio/index.html - there is room for optimization, I think I can optimize away 2 TTL chips, even without sacrificing the fact that it can actually run as a _drive_ on the IEEE488 board due to its ATN Acknowledge circuit. Also, the IEEE488 connector is basically unobtainable... the next version will have card edge connectors, plus flat ribbon cable connectors, but no real IEEE488.
I don't have tape drive transistors, but still 5V for hopefully the "usual" extensions.
The next version will also have an additional 74HCT245 as voltage converter between CPLD and CPU.
I just hope to stay under the limit of a Eurocard (160x100mm) as this is what my version Eagle can do max (an old not-for-profit version).
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"Super MiniPET" comes to mind, but I'm sure we all see how that could get confusing. Unless you care to add a 6809 to the board?
Haha. No that chip is too slow
Du you know about the Micro-MMF (uMMF)?
Btw: here's an update video:
https://youtu.be/7ZddamWx9IoAndré
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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content:
http://6502.org/users/andre/