Some of the apparent differences between the 6510 and 7/8501 are actually board-motivated: for example, (intriguingly) there is no way to generate an NMI on the Plus/4, and probably any other 264 series computer, despite the fact the 7501 does accept NMI signals.

The datasheet shows a GATE IN pin, but seems to have no description of it. The block diagram does conspicuously omit /NMI from the inputs to the interrupt block, though.

A control line is provided (GATE IN) to hold off the R/W line until /RAS makes the transition from low to hi. This prevents the Read line from making an early transition to the write state which would cause an improper Early Write Cycle to occur.
GATE IN - TTL level input, used to gate the R/W line to prevent the R/W line from going low during a read cycle, before RAS and CAS so high (resulting in a Read/Write cycle). Normally connected to the MUX line in a system configuration to synchronize the DRAM memory cycle to the processor clock cycle.

GATE IN seems to be related to the DRAM control in the 264 series. The 7360/8360 (TED) handles DRAM refresh (Drives /RAS and /CAS, which are wired to U5 and U6 in the C16 schematic). The MUX line is driven by the TED and is wired to GATE IN on the CPU.

Is the 7501/8501 used in any computers other than the 264 series?

I think I read somewhere that the NMI circuitry is still on the die in the 7501 but not bonded out to a pin?