My project with a w65c265s MCU.

[BigEd]

> Did I mention that I have to learn 6502 programming to get this to do something??

A grand adventure!

[tokafondo]

Dr Jefyll wrote:

And I'll bet you can use the values stated on the schematic -- no need for variable caps. Good luck!

Well... actually, I'm running FCLK with no capacitors at all. IDK why, but leaving the ones that schematic showed made the MCU unable to make the ~5Mhz crystal run. So I think I will have to get caps with values nearest to the ones that the trim caps I previously had, had.

Or put the trimmers again. I had the MCU running stable for about 9 hours and then freezed, so I can't tell that part is done.

I think I'm testing the 6Mhz output the FTDI232 provides...

[Dr Jefyll]

This looks quite a lot better. But in the 2nd photo, are those bare wires leading away from the upper right corner of the '265 ?? A wrapping experiment, perhaps? -- something you'll remove later?

[tokafondo]

Dr Jefyll wrote:

This looks quite a lot better. But in the 2nd photo, are those bare wires leading away from the upper right corner of the '265 ?? A wrapping experiment, perhaps? -- something you'll remove later?

Not bare but thin black insulated wires that were what my local electronics store have for sale. I can't tell exactly because the didn't knew. Maybe 22 AWG or something. They carry the serial data lines.

[tokafondo]

I decided to rearrange my geek room, and also decided to rearrange the SBC.

As I received the final items for the first part of the project (128K of 55ns RAM, the EEPROM and its socket, the 74HC00 chips...) I decided to move the MCU to the left.

So I have to desolder everything, rearrange the bottom part of the SBC to have as much as possible under the MCU itself, and put the reset button in a corner.

The board itself got a bit burnt because I used a heat gun to get all the soldered pins liquid at once.




I also got rid of the pins, because I just couldn't get the ability to wire wrap the right way -- also, the space was so full of pins that for me it was a no-brainer to take them away.

It's waaaay cleaner than before.

[tokafondo]

PROGRESS:

I've added a second serial port to my board, as I intend to implement Andrew Jacob's w65c265sxb-hacker tool.

I also have added a 74hc00 there, just at the left of the MCU.

I'm modelling this prototype after the w65c265sxb, and now I'm going to add both the EEPROM socket and the SRAM socket.

I have two questions:

1.- Is is better to arrange the DATA and ADDRESS cables in parallel or in a star configuration?

Code: Select all

PARALLEL
--------
[MCU] -> [EEPROM] -> [SRAM] -> [VIDEO CHIP] (when implemented).

STAR
----
         [VIDEO CHIP]
      (when implemented)
             /|\
              |
[EEPROM] <- [MCU] -> [SRAM]

2.- The w65c265sxb originally comes with 32K of SRAM. But the chip I got is 128K. I've seen the 32K wired in the SXB schematics with all the ADDRESS and DATA bus pins. Does it mean that all the chip will be enabled when selected, or only its first 32K of RAM, as the original SXB does with its 74HC00?

Thanks for replying.

[BitWise]

You can make my hacker tool work with the same UART as the monitor or a different one. It is controlled by the UART equate in the w65c265sxb.asm file.

How much RAM you can see will depend which chip select line you drive it from. CS3B (e.g /CS3) selects $0200-$7FFF in bank zero ($0000-$01FF is provided by the chip). If you use CS7B (/CS7) then you can have upto 4M at $C0:0000-$FF:FFFF (or a smaller amount repeating).

I had a try using with CS5B but without much success. I've not spent long try to find out why. It may not be enabled by default.

[tokafondo]

Thanks! As I'm cloning the SXB design, the schematics show that its /CE input is driven by CS3B and, and I'm correcting my mistake here, its address inputs are driven from A0 to A14, so that means 32768 bytes for me.

So, my question was that if even putting a 128K chip there, wiring only from A0 to A14 would render the chip to just use 32K.

Anyway, the goal here would be to have a SBC with a custom ROM that, once enabled by the internal monitor, would disable the internal RAM and ROM at all and take full control of the MCU, having it access to the full 128K of RAM.

In my design, a video chip with additional 384K of ram is to be implemented, so I know that at some point a CPLD will be a must there.

[Martin A]

tokafondo wrote:

So, my question was that if even putting a 128K chip there, wiring only from A0 to A14 would render the chip to just use 32K.

You will still need to connect A15 and A16 on the 128k ram to 0v or 5v. Which you pick doesn't really matter as long as they're not left floating.

[BitWise]

tokafondo wrote:

So, my question was that if even putting a 128K chip there, wiring only from A0 to A14 would render the chip to just use 32K.

You can only have 32K driven by CS3B.

The datasheet seems to suggest that you could disable CS3B generation and have the one 128K RAM chip cover $00:0000-$01:FFFF using CS5B but some regions will map to chip based memory unless you disable more signals.

I tried programming the PLD on my 1MB SRAM board to use CS5B but it didn't work and I've not had the time to work out why. I use CS7B as it works reliably.

[tokafondo]

Martin A wrote:

You will still need to connect A15 and A16 on the 128k ram to 0v or 5v. Which you pick doesn't really matter as long as they're not left floating.

Directly? No resistors or something?

BitWise wrote:

The datasheet seems to suggest that you could disable CS3B generation and have the one 128K RAM chip cover $00:0000-$01:FFFF using CS5B but some regions will map to chip based memory unless you disable more signals.

I tried programming the PLD on my 1MB SRAM board to use CS5B but it didn't work and I've not had the time to work out why. I use CS7B as it works reliably.

So... I wouldn't be connecting P73_CS3B_SRAM to VDD, but P75_CS5B instead?

SXB Datasheet wrote:

Note 2 - When on-chip ROM, CS3B and/or CS4B are enabled:
a.) CS5B decode is reduced by the addresses used by same.
b.) CS0B and CS1B address space never appears in CS2B, CS4B or CS5B decoded space.

Would this mean that if I enable CS5B instead of CS3B, the first 128K of RAM would start from 00:0000, and the internal chip memory locations, registers and ROM would still apply?

I also don't understand why should I enable CS2B as it's enabled by default... But I will do it anyway.

[tokafondo]

BitWise wrote:

You can make my hacker tool work with the same UART as the monitor or a different one. It is controlled by the UART equate in the w65c265sxb.asm file.

I'll have to work with it as it is until I've learnt enoguh for that kind of modding.

One question: Will I be able to flash your rom in one of the EEPROM 32K banks, so I won't have to upload it every time I boot the board?

[GARTHWILSON]

tokafondo wrote:

Martin A wrote:

You will still need to connect A15 and A16 on the 128k ram to 0v or 5v. Which you pick doesn't really matter as long as they're not left floating.

Directly? No resistors or something?

The only reason to use resistors would be if you might later want to drive them with something and not have to cut traces or wires to do it. If you never will, then you can wire them directly.

[tokafondo]

Hi. Request for help again.

In the W65C265SXB schematics, we have that

P72_CS2B
P73_CS3B_SRAM
P74_CS4B_FLASH

are tied to +5V trought LED and then a 3K RESISTOR in serial.

I would like to know if doing that is what tells the '265 that there is a SRAM and a FLASH chip present.

Because I wired my board exactly like that, and when I read the 00:DF27 register, I always get FB (11111011).

I wired the memory as in the schematics, but when I modify one single memory location, and then read it again, I get that not only that single memory location has changed, but all the following ones.

==========
Example:

I use the D command to display memory contents between 0200 and 02FF. It replies 9C 9C 9C ... 9C.
Then, I use the F command to fill that memory locations (0200-02FF) with 00.
Then, I use the D command again to display memory contents between 0200 and 02FF. It replies 00 00 00 ... 00.
Then, I use the M command to change the memory contents, starting from 0200. And I put E0 in that single memory location (0200).
Then, I use the D command again to display memory contents between 0200 and 02FF.

The expected reply should be: E0 00 00 00 ... 00.

But the reply I get is E0 E0 E0 E0 ... E0.
==========

I'm working with 3.3V instead of 5V as the schematics are shown, and I like to know if the RESISTOR values should be modified.

[Chromatix]

The key question you should investigate is whether those pins are configured as inputs or outputs. The presence of LEDs suggests they may be outputs.