Question about simplifying this circuit for Read cycles

[rascalsailor]

With reference to this 6502 minimal chip count schematic of Grant's from http://searle.x10host.com/6809/Simple6809.html, is there any reason why the ROM, U4 output enable (/OE) cannot simply be grounded? (Perhaps the Ram as well)
i.e. the ROM is accessed whenever A14 and A15 both go high. (Ram access when A15 low)
I can't any problems with that. Read data would be valid when the Phi2 clock strobes low. Right?
Regards
Russell

[Dr Jefyll]

Ideally, the first half of every cycle (Phi2 low) is a period during which no device (neither RAM / IO nor the CPU) drives the data bus, and I believe authoritative sources (MOS Technology, WDC) endorse this. No data transfer occurs during Phi2-low anyway, and it's better that this period be a "dead time" to act as a timing cushion. Remember, control of the bus is constantly getting passed back and forth between devices. Without the dead time you need to either perfectly time the control signals to the devices (impractical) or tolerate a brief (small fraction of a cycle) period of bus contention as two devices collide during the handover.

Often the contention can be tolerated, but there's a tradeoff involved re noise and power dissipation if not actual reliability. It's good practice to use a gate as Ben has done. Hope this helps,

Jeff

[rascalsailor]

Hi, thanks for the reply. Yes that sounds like a better practice. Reducing the contention sounds like a good reason to keep it in circuit.
regards
Russell

[GARTHWILSON]

The address-decoding page of the 6502 primer shows the simplest methods. If 32KB of ROM and 16KB of RAM and up to ten I/O ICs is enough, you can do the whole thing with a single 14-pin quad NAND gate and even have one section left over; so if you make it a Schmitt-trigger type, you can use that last section for the reset circuit as shown in the first diagram in the circuit potpourri page. The diagram there shows different clock-oscillator options, EPROM versus EEPROM, IRQ\ versus NMI\, etc., so be sure to refer to the notes underneath. On the ROM, it does show the OE\ connected to the CS\; and on the RAM, part of the secret is that the OE\ is connected to A14, meaning that when you write to I/O, you're also writing to the half of the RAM you're not using, but when you read I/O, the RAM's output is disabled, so there's no bus contention. This is not the very fastest method, particularly for RAM set-up; but RAM is available in faster speeds than the other things on the bus anyway, so it probably won't matter. (I've seen SRAM down to 6ns.) On most SRAMs, OE\ is a "don't care" if WE\ is low. If you want 16KB of ROM and 32KB of RAM, you'll need one more IC, as shown further down on the address-decoding page.

Quote:

Read data would be valid when the Phi2 clock strobes low. Right?

A cycle starts with phase 2 low, which is when the processor is setting up the address and R/W lines. The second half of the cycle is when phase 2 is high, and that's when data are transferred on the data bus.

[rascalsailor]

Thanks for that. Another curiousity; I often see the /oe and /cs of the rom driven together, but wouldn't you get faster device access if you permanently assert /cs and only drive /oe from your decoding logic? According to the data sheet /oe is faster for data output enable.

[Dr Jefyll]

Quote:

wouldn't you get faster device access if you permanently assert /cs and only drive /oe from your decoding logic?

Yes you would, but it's a tradeoff in terms of power consumption because asserting /CS wakes up the chip, bringing it out of its low power standby mode. Typically you'd prefer to have the chip sleep when it's not being accessed.

Stuff you've seen in circuits doesn't always have a reason, btw. If /OE is tied to /CS then it would've been just as good to tie /OE to ground. But maybe the PCB layout was such that the designer found it easier to attach to /CS.

Often (as in Ben's circuit) you'll see /CS driven from the address decoder and /OE driven by /Phi2 or R/W qualified by Phi2, and this arrangement accommodates the slower response of /CS because the decoder will have a valid signal during the first half of the cycle before Phi2 transistions.

[rascalsailor]

Thanks for the reply.

[Dr Jefyll]

You're welcome.

As an incidental point, this business about trying to get /CS enabled before /OE has diminished relevance where modern RAMs are concerned. Many of them are so fast it's acceptable to let /CS wait until Phi2 rises, and that's an approach that may simplify your glue logic.

-- Jeff