With reference to this 6502 minimal chip count schematic of Grant's from http://searle.x10host.com/6809/Simple6809.html, is there any reason why the ROM, U4 output enable (/OE) cannot simply be grounded? (Perhaps the Ram as well)
i.e. the ROM is accessed whenever A14 and A15 both go high. (Ram access when A15 low)
I can't any problems with that. Read data would be valid when the Phi2 clock strobes low. Right?
Regards
Russell

Ideally, the first half of every cycle (Phi2 low) is a period during which no device (neither RAM / IO nor the CPU) drives the data bus, and I believe authoritative sources (MOS Technology, WDC) endorse this. No data transfer occurs during Phi2-low anyway, and it's better that this period be a "dead time" to act as a timing cushion. Remember, control of the bus is constantly getting passed back and forth between devices. Without the dead time you need to either perfectly time the control signals to the devices (impractical) or tolerate a brief (small fraction of a cycle) period of bus contention as two devices collide during the handover.

Often the contention can be tolerated, but there's a tradeoff involved re noise and power dissipation if not actual reliability. It's good practice to use a gate as Ben has done. Hope this helps,

Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hi, thanks for the reply. Yes that sounds like a better practice. Reducing the contention sounds like a good reason to keep it in circuit.
regards
Russell

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks for that. Another curiousity; I often see the /oe and /cs of the rom driven together, but wouldn't you get faster device access if you permanently assert /cs and only drive /oe from your decoding logic? According to the data sheet /oe is faster for data output enable.

Yes you would, but it's a tradeoff in terms of power consumption because asserting /CS wakes up the chip, bringing it out of its low power standby mode. Typically you'd prefer to have the chip sleep when it's not being accessed.

Stuff you've seen in circuits doesn't always have a reason, btw. If /OE is tied to /CS then it would've been just as good to tie /OE to ground. But maybe the PCB layout was such that the designer found it easier to attach to /CS.

Often (as in Ben's circuit) you'll see /CS driven from the address decoder and /OE driven by /Phi2 or R/W qualified by Phi2, and this arrangement accommodates the slower response of /CS because the decoder will have a valid signal during the first half of the cycle before Phi2 transistions.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks for the reply.

You're welcome.

As an incidental point, this business about trying to get /CS enabled before /OE has diminished relevance where modern RAMs are concerned. Many of them are so fast it's acceptable to let /CS wait until Phi2 rises, and that's an approach that may simplify your glue logic.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html