My6502 - A 74-Series 6502

[vfxsoup]

Hi all. Hope you're all doing OK.

It's been quite a while since my last update but I wanted to start getting some of the schematics and PCBs on here for thoughts and comments. Things are progressing quite nicely with the project - I have schematics for the Register, Status Register, ALU, Buffers & Constants and the Control Unit, and running alongside I've made some more improvements to the emulation.

I was struggling somewhat with the practicalities of how all this would fit together. The idea all along was for a long "bus board" that would have tracks for each of the five buses (Read, Write, Data, Address Low and Address High), as well as power, ground and clock signals. Each card would have right-angled headers that would push into sockets, and the control signals would come via ribbon cables from the Control Unit boards. However looking at the cost of building the cables, and the sockets for each, not to mention the room on the already very congested CU boards I figured that a card-edge connector might be a more elegant solution. I found these PCI-E style (albeit larger pitch) sockets on Toby https://www.toby.co.uk/board-to-board-p ... ge-socket/, which have 120 contacts - enough for all the power, buses, clocks and control signals. So I redesigned the register card to use an edge connector that would fit such a socket and it all seems to work quite nicely in theory.

So here's the schematic and a screengrab of the PCB layout for the Register card, along with the little daughterboard that converts the registers into counter registers.

16-bit Generic Register Card Schematic

16-bit Generic Register Card PCB layout

The text reads for the Register card:

Quote:

This is a generic double register board capable of being configured for A+T, X+Y, PCL+PCH, ADL+ADH, and S.
Register A (top) can output to the Read Bus (RB) or the Address Low Bus (ADLB);
Register B (bottom) can output to the Read Bus or the Address High Bus (ADHB). In some cases (A, T, X and Y) only the A-RB and B-RB output buffers are required, since these registers don't need to access the Address bus.
On-board 74HC377 ICs are used for the static registers A, T, X and Y due to their Load Enable pins.
A daughterboard with 2 x 74HC161 (up-only counters like PC) or 2 x 74LS169 (up-down counters for the stack) can be attached via headers for the counter registers. In such instances the 74377 ICs aren't used.
Outputs are buffered using either 74HC245 ICs configured to output A-B, or 74HC541 ICs, which share an almost identical pinout.
Jumper JP1 is used to set which IC is used (at present all output ICs must match).
In the case of the Stack pointer, 74HCT245 ICs are used for the output buffers to cope with the reduced voltage signals from the 74LS169 chips.
Solder-bridge jumpers are employed to select which registers are being built, as all control signals are available to the card via the edge connector.
Two 9-pin headers are used to connect a small LED display board if required when running in slow or single-step mode, to view the current value of the register.

Counter Register Daughterboard schematic

Counter Register Daughterboard PCB Layout

And for the daughterboard:

Quote:

This daughterboard converts a single 8-bit register to a counter register. It uses either 2 x 74HC161 4-bit counter ICs (for up-counting registers like the Program Counter),
or 2 x 74LS169 4-bit up/down counter ICs for the Stack Pointer.
Carry Out (COUT) and Carry In (CIN) headers are available to provide ripple carry for 16-bit registers.
The 2.2k resister network pulls any high outputs of the 74LS169 ICs up to 5v. However this may not be required if using 74HCT245/541 ICs as the output buffers on
the main register board.
The short SH1 is used to tie both Count Enable pins to the single COUNT control signal. This is cut if the register is the upper byte of the 16-bit word to use the CIN signal instead.

Regarding clocks, the CLK signal is a 3.125MHz PHI0 (I guess) that contains both half-cycles PHI1 and PHI2 (1.5625MHz). PHI1 and PHI2 are available but only used by certain boards. In this implementation everything is done on the rising edge, since most 74 flip-flop logic uses the rising edge to latch data.

I'm 90% convinced that the edge connector is the way to go, but as yet haven't updated the other cards with the new connector, so I'll hold off uploading them for now. In the meantime I'd love to hear your thoughts on any of this. PCB layouts should be taken with a pinch of salt - the silkscreen info is barely started and I'll need to print them out and try components for spacing, etc.

Christian

[vfxsoup]

Folks - a quick opinion poll if I may.

I'm concerned that my current design, which features a backplane with 10-or-so cards stacked up using PCIe x16 interconnects (yes, that's different from what I posted earlier - long story short, 120 pins on the smaller sockets wasn't going to cut it) is going to be
a) very expensive, having 7 different eurocard PCBs made up, and also 3 daughterboards, not to mention the backplane itself, and the sockets, etc.
b) possibly restrictive on clock speed, due to noise issues, etc.

Would you advise against doing it this way, instead building a single board version? I can get a large (350x300mm) board made up for about £75 ($90) delivered, which would accommodate all the ICs and supporting components comfortably. The only downsides I can see are that
a) it's gonna be a very challenging PCB route
b) if there's a horrific error it's more expensive to re-spin the card than it would be to do one of the eurocards in my current design (bodge wires excepted!)

Thanks! Christian

[BigEd]

My gut feeling is that modular is better - the question is whether you can slice the thing at its joints.

[Dr Jefyll]

vfxsoup wrote:

Would you advise against doing it this way, instead building a single board version?

Rather than a rigid back plane, I'd at least consider using ribbon cable instead. I mention some advantages here.

cheers
Jeff

[vfxsoup]

BigEd wrote:

My gut feeling is that modular is better - the question is whether you can slice the thing at its joints.

Thanks. I've got things modularised currently, so no real issue with what goes on which board, the problem I'm trying to solve is how to transmit the bus, clock and control signals efficiently and cleanly.

Dr Jefyll wrote:

Rather than a rigid back plane, I'd at least consider using ribbon cable instead. I mention some advantages here.

Interesting, thanks. I have 5 8-bit buses, 72 control lines, power and clock signals, so in all about 120 lines. You mention that "it's strongly recommended that ground lines be interspersed with the signal lines". Ideally I guess that every one of those lines would have a ground return, so 240 wires. I don't know if that's possible for any kind of backplane, rigid or flexible. The PCIe x16 connector has 164 pins, which means many of my signals have to share ground returns (e.g. in my current design, the buses each have 4 ground returns per 8 bits).

One solution could be to just run the buses through the backplane (looks like you can get 80-wire ribbon cable), then power separately, and clocks and just the required control signals to each board. That seems like a lot of different cables and connectors, and could be expensive & cluttered. I'll probably need to rethink the overall layout too, having a larger "motherboard" with the power, clock, control unit and interrupts on board, then stack up the modular cards (registers, ALU, buffers & constants, memory?). It's all rather difficult to get my head around...

Apologies for being so green! I'm probably approaching this all wrong so all advice gratefully accepted.

Thanks, Christian

[Chromatix]

You don't have to pair every single signal line with a ground line. Just make sure that the shortest return path doesn't deviate too much from the signal path for each signal. I think it might be reasonable to ensure there's a ground wire on both sides of each 8-bit bus, for example, and even then you can share them with adjacent buses.

[Dr Jefyll]

Chromatix wrote:

You don't have to pair every single signal line with a ground line. Just make sure that the shortest return path doesn't deviate too much from the signal path for each signal.

Right. Having far fewer grounds than signals is a reasonable compromise. Just remember some signals are more critical than others. Clock signals, for example, deserve placement in the preferred locations next to ground lines.

BTW, in this context the lines carrying your +5 power can also be considered ground. Just be sure each of these lines connects to an AC ground -- a bypass cap to actual ground -- somewhere close to where the line enters the card.

Quote:

looks like you can get 80-wire ribbon cable

Myself, I'd consider two 40-wire cables instead, just because I find the super-wide connectors tough to plug and unplug. But maybe you won't be doing that much. And admittedly the two-connector option occupies somewhat more space.

-- Jeff

[BillG]

Dr Jefyll wrote:

Chromatix wrote:

looks like you can get 80-wire ribbon cable

Myself, I'd consider two 40-wire cables instead, just because I find the super-wide connectors tough to plug and unplug. But maybe you won't be doing that much. And admittedly the two-connector option occupies somewhat more space.

It may be worthwhile to go with a 50-wire cable and a 30-wire one to avoid plugging them in the wrong place. If using two 40-wire cables, put the indexing pins in different locations.

[GARTHWILSON]

As others have said, it shouldn't really be necessary to have a ground wire for every sigle signal wire. If every signal wire runs next to a ground (or Vcc bypassed to ground at the connectors) wire, that's almost as good, and takes you from 240 wires down to 180. So you'll have for example sGssGssVssGssGssVssGssGs Where s is signal, G is ground, and V is Vcc bypassed to ground at the connector pins.

To get a better concept of what's going on there, see the post, with illustrations, at viewtopic.php?p=55094#p55094 . In any case, clock lines are the most critical to keep clean.

[vfxsoup]

Thanks for the responses, all.

Am I correct in assuming there's nothing electrically advantageous to using ribbon cable over edge connectors/sockets? Is it more an ease of use kind of thing? Dr Jefyll, you suggested that it might be cheaper to run ribbon cable. I can get 10xPCIe16 sockets for £22 including tax and shipping. That would basically give me all my buses, clocks and control signals in one hit (granted, with the PCIe connector being 1mm pitch it would be one heck of a routing job!). I haven't looked into ribbon cables properly yet, but from what I've seen so far it looks a lot more expensive to buy connectors, sockets and the cable.

Anyway I'm going to give it some proper thought. Thanks for the suggestions.

Christian

[GARTHWILSON]

Christian, IDCs (insulation-displacement connectors) for ribbon cables, and the matching pin headers to mount on the PCBs, are very inexpensive. The IDCs are quick and easy to mount on ribbon cables, requiring only a vise or other tool to mash them onto the ribbon. You can put as may IDCs on one ribbon as you like. A benefit of a backplane PCB would be if you do an actual ground plane (and no, copper pours do not qualify). A benefit of ribbon would be that you can rotate the boards apart for probing (since the ribbon is flexible); but if you make the ribbon substantially longer, that length may make it a little harder to get the needed AC performance.

[BillO]

GARTHWILSON wrote:

(and no, copper pours do not qualify).

What about the case where the copper pour is contiguous under the backplane traces and grounded, (which is entirely possible)? Well, I guess that is actually a just a ground plane ... never mind...

[BigDumbDinosaur]

Dr Jefyll wrote:

Quote:

looks like you can get 80-wire ribbon cable

Myself, I'd consider two 40-wire cables instead, just because I find the super-wide connectors tough to plug and unplug. But maybe you won't be doing that much. And admittedly the two-connector option occupies somewhat more space.

How about 50-conductor cable as used in "narrow" SCSI interfaces?

[daniMolina]

Beware of the 80 wires / 40 pins cables, designed for the old PATA interfaces. I was planning to use one of those in my 74HCT6526 but they have one hidden problem..

Yes, every other wire is GND, but they are all connected to the pins that are tied to ground in the IDE interface.

There are 7 of those in the interface so, unless your design has those 7 pins connected to GND, you'll run into problems the moment you turn the power on. This doesn't mean they're unusable of course, but you are down to only 33 pins.

Substract one additional pin, as pin 20 is unused, and generally blocked, to be used as a key for the connector.

[vfxsoup]

Hi all,

Thanks for the responses and info regarding connectors. All very helpful.

Having run them past him and made some changes following his advice, Dieter has recommended I post the schematics here for wider comment. So here goes!

First the Control Unit. This is the circuit that's changed the most and had a considerable diet, shedding about 10 ICs in the process. It also has clock generation and interrupt detection. The clock is the least developed part at the moment - I'm struggling with how to do single step and single instruction; The clock is derived from a 25MHz oscillator, which will be the VGA pixel clock. The CPU will run at 3.125MHz, with each half-cycle being 1.5625MHz. The microcode will be stored on 2x16-bit ROMs that, in the first instance will be Flash memory. I've also included the daughterboard schematic and PCB layout for the Flash memory, which is the only SMD part of the whole project at the moment. (The reason for the Flash is that the only 16-bit DIP ICs I can get are write once EPROMs, and therefore errors in programming will be costly!)

My6502 - Control Unit

My6502 - ROM Daughterboard (Flash version)

Daughterboard PCB Layout

Next up is the Register board, which has changed from what I posted before. Now all registers, including the Status Register are on one board.

My6502 - All Registers

The ALU is based on Dieter's multiplexer design. There's a config to use the B-Input Register, or not, as per my current emulation. If I find that there are timing errors due to contiguous memory access & ALU processing, I can rejig the microcode and use the B-Input Register instead.
Currently an ALU process goes something like this:

Code: Select all

Step 1 PHI2 - ADL_OUT, ADH_00 // Zero-page access - memory read onto DB
              ALU_L_A, ALU_R_2, ALU_R_3 // Load Left side with the RB, Load Right Side with the DB; ALU latches result in output register
Step 2 PHI1 - ALU_OUT, A_LOAD // Output ALU output regsiter onto WB, Load WB into Accumulator

but it would change to:

Code: Select all

Step 1 PHI2 - ADL_OUT, ADH_00 // Zero-page access - memory read onto DB, automatically latched into B-Input Register
Step 2 PHI1 - ALU_L_A, ALU_R_2, ALU_R_3 // Load Left side with the RB, Load Right Side with the DB
              ALU_OUT, A_LOAD // Output ALU onto WB, Load WB into Accumulator

So no change in execution time, just which half-cycle the ALU setup happens.
You'll also see that there's currently no Decimal conversion on the ALU. It was never something I'd intended to implement, however I have got SED/CLD implemented so it could be retrofitted somehow (perhaps a daughterboard, so tips on where that could go would be great), or the board revised.

My6502 - ALU

Finally for now are the Buffers and Constants, for bus-to-bus transfer, and zero-page/stack/interrupt address generation.

My6502 - Buffers and Constants

I'm thinking a stack of 3 cards, probably around 200x160mm in size. That will let me do board-to-board relatively easily with ribbon cables and/or pin headers.
A lot to digest! Hope it makes sense and as usual I'm all ears for suggestions, improvements and errors.
Thanks, Christian