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PostPosted: Wed Jul 10, 2019 12:47 pm 
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Some days ago I created an overlay of my (admittedly bad quality) die shot of the

8500R4 (aka 6510) and 8501R4.

I'm quite sure that the 6510 was developed BEFORE the 8501... but
the layout of the later 8500R4 seems to be derived from the 8501R4
or maybe they created them with having the variants already in their minds?!

But better see yourself (please be patient while it loads):

https://is.gd/rgcifA

Please note the metal lines at the right part of the chip:

Attachment:
850x.jpg
850x.jpg [ 319.52 KiB | Viewed 2974 times ]


Doesn't really make sense for the 8500... that's why I think the 8501 came first!

Does someone have shots of the MOS8502? I'd bet it's the same except the I/O port section.


Last edited by fhw72 on Wed Jul 10, 2019 1:11 pm, edited 5 times in total.

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PostPosted: Wed Jul 10, 2019 12:53 pm 
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No real layout comparison... but maybe someone wants to take a look at the

Metal and Poly layer of the MOS8360R2 aka "TED"

from the Commodore C16/plus4 line of computers: https://is.gd/ZC6VrT

Or the 6509R7 CPU: https://is.gd/spxeF5


Enjoy the slide.... :D


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PostPosted: Wed Jul 10, 2019 1:14 pm 
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Interesting finding and an interesting tool for comparisons...

I wonder when CSG got computer aided design? It's possible to copy and paste once your layout is vectors in a computer - but the original 6502 was a ruby-lith layout done with sharp knives. So, at some point, I'd suppose, MOS/CSG would have digitised that layout and started on a journey of making derived designs.

Is it possible that the 6510 was its own thing at the time but the 8500 was a later recreation? It's surprising (to me) that the 8500 has 8 bits of I/O port logic, with 8 pads, but only 6 pads bonded. Was there a chip which used all 8 bits of the port? Or a plan for such a chip?


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PostPosted: Wed Jul 10, 2019 1:20 pm 
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The 8502 used more bits of the port (7 bits)!


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PostPosted: Wed Jul 10, 2019 1:33 pm 
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Here's a comparison of the 6510 and 8500:

https://is.gd/ad5OyB

Please note that the main core in the middle is the same size (proportionally) but the outer
perimeter (i.e. drivers, ports etc.) are stretched vertically - a little bit.

PLA/Decode rom is also perfectly aligned!


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PostPosted: Wed Sep 11, 2019 9:02 am 
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Did you ever want to skin the CIA? :D

https://is.gd/Qsy6lh


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PostPosted: Wed Sep 11, 2019 11:08 am 
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Nice! Are there any bugs or idiosyncrasies in the 6526 which might inspire a look at the transistor netlist?


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PostPosted: Wed Sep 11, 2019 12:53 pm 
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BigEd wrote:
Nice! Are there any bugs or idiosyncrasies in the 6526 which might inspire a look at the transistor netlist?


Yes... I want to check the *EXACT* differences between the 6526R4 and the successor 8521R1 (which was labeled 6526 as it's identical
in fucntionality but has some differences in the interrupt control).


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PostPosted: Tue Sep 24, 2019 1:34 pm 
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I redid the 8500R4 vs. 8501R4 comparison:

Vertical slider: https://is.gd/8ECZRp

Horizontal slider: https://is.gd/ZWHAMC


Enjoy!


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PostPosted: Fri Sep 27, 2019 7:20 am 
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Location: Madrid, Spain
Beautiful!


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PostPosted: Fri Sep 27, 2019 1:46 pm 
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daniMolina wrote:
Beautiful!


Then you might like this one too:

https://is.gd/ivRQTB

It's the overlay of metal and poly layer.


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PostPosted: Thu Dec 05, 2019 7:43 am 
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Someone wanted to know the differences between

MOS8501R1 <-> MOS8501R4

Here we go:

https://is.gd/6fcY1U

GATEIN Logic seems untouched. What I can see so far:

MOS8501R1 still has the (unused!) SYNC pin logic (moved between pads for NMI# and IRQ#).
This logic was replaced with a back bias generator.


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PostPosted: Fri Dec 13, 2019 12:54 pm 
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Yet another one just finished:

MOS8726R1

https://is.gd/fk6HzZ


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PostPosted: Mon Dec 23, 2019 9:25 pm 
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In order to dig a little deeper in the 6522R0 I restitched the publicly available pictures
of the 6522R0 and realigned metal and poly layer:

https://is.gd/WM2hJr


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PostPosted: Thu Jan 16, 2020 4:27 pm 
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And here another one:

https://is.gd/lZ4IZn


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