65x02 variants

[tomaitheous]

First off I wanted to say this site it great. It's a treasure trove of 65xx information.

I wanted to know if anyone is documenting the 65xx variants. I'm currently working with a 7.16mhz HuC6280, a 65c02 Rockwell variant (with the extra RMBi,SMBi,TRB,TSB,etc opcodes) made by Hudson.

Just a quick list of features..

Swap register instructions - SAY, SAX, SXY. They don't effect flags, so it can be useful for using two regs to do 16bit adds or shifts.

Branch instructions that cross a page boundary don't have a penalty cycle.

Store immediate(byte) instructions ST0, ST1, ST2. Though they only correspond to three static addresses.

TST #nn, <ea> - ea is ZP, ZP,X , ABS, ABS,X. ANDs the immediate with the corresponding address and updates the flags. EDIT: Results are discarded.

Block transfer instructions TII,TDD, TIA, TAI, TIN. I is increment, D is decrement, A is alternate (for writing/reading a word size port), N is static (for byte size port). 17cycles to setup, 6 cycles per byte, and can transfer up to 64k. Interrupts are delayed until the transfer is complete.

The CPU has an external 21bit address bus. The internal 16bit address range is divided into 8k pages. There are 8 internal page registers labeled MPRx. which correspond to each $2000 bytes of the address range. Two transfer instructions are used to update the MPR register- TAM and TMA (using the A reg). Any bank can be mapped to any page, including a single bank to multiple pages. The IRQ vector addresses are set to the CPUs logic address map and can be swapped out by changing the bank for MPR7 (page $e000-ffff).

SET - set the T flag. The T flag is right between the V and B flag. When the T flag is set, the value in the X reg is a pointer to zeropage. Any arithmetic or logic instruction will use the ZP address pointed by X instead of the A reg, and store the result in the ZP location - leaving A unchanged. Unlike the mitsubishi e740, every instruction clears the T flag. So you have to SET right before every arithmetic or logic instruction (that means SEC, CLC, or SED before SET).


-Rich

[GARTHWILSON]

Welcome. These are pretty interesting instructions (although all the 65c02's made today have the SMB, RMB, BBS and BBS instructions, and are all rated for at least 14MHz). I don't know a direct answer to the question about whether anyone has documented all the '02 variations, but the 65816 only costs about a dollar more than the '02 and does all this and a lot more. For new projects, there's practically no reason to use the '02 instead of the '816. You can download the programming manual, free, on Western Design Center's website.

[fachat]

tomaitheous wrote:

First off I wanted to say this site it great. It's a treasure trove of 65xx information.

So I assume you already found
http://www.6502.org/documents/datasheets/
with information about the different 6502 variants.

Quote:

I wanted to know if anyone is documenting the 65xx variants. I'm currently working with a 7.16mhz HuC6280, a 65c02 Rockwell variant (with the extra RMBi,SMBi,TRB,TSB,etc opcodes) made by Hudson.

the URL above is my normal source, plus this Commodore-related page
http://www.zimmers.net/anonftp/pub/cbm/ ... index.html

The chip has interesting features, esp.

Quote:

The CPU has an external 21bit address bus. The internal 16bit address range is divided into 8k pages. There are 8 internal page registers labeled MPRx. which correspond to each $2000 bytes of the address range. Two transfer instructions are used to update the MPR register- TAM and TMA (using the A reg). Any bank can be mapped to any page, including a single bank to multiple pages. The IRQ vector addresses are set to the CPUs logic address map and can be swapped out by changing the bank for MPR7 (page $e000-ffff).

which reminds me of my own system with MMU http://www.6502.org/users/andre/csa although my MMU is external.

Quote:

SET - set the T flag. The T flag is right between the V and B flag. When the T flag is set, the value in the X reg is a pointer to zeropage. Any arithmetic or logic instruction will use the ZP address pointed by X instead of the A reg, and store the result in the ZP location - leaving A unchanged. Unlike the mitsubishi e740, every instruction clears the T flag. So you have to SET right before every arithmetic or logic instruction (that means SEC, CLC, or SED before SET).

So the "SET" works like a kind of "prefix" as in other architectures, to modify an opcode. What about the X-indexed addressing modes?
what would

Code: Select all

SET
ADC $02,X

do?

Is this chip still available?

André

[kc5tja]

tomaitheous wrote:

SET - set the T flag. The T flag is right between the V and B flag. When the T flag is set, the value in the X reg is a pointer to zeropage. Any arithmetic or logic instruction will use the ZP address pointed by X instead of the A reg, and store the result in the ZP location - leaving A unchanged. Unlike the mitsubishi e740, every instruction clears the T flag. So you have to SET right before every arithmetic or logic instruction (that means SEC, CLC, or SED before SET).

I think this needs to be re-explained. The 6502 and 65816 both lack any instruction which touches memory through the A register. The contents of A are transferred to memory during a store, and is therefore unaltered anyway. However, there are no instructions where the A register itself is used to index into memory.

This also holds for the 65816 block move instructions, where A is a counter, not an index. The X and Y registers are used for the actual pointer values.

Thanks.

[tomaitheous]

normal code:

lda <$30 ; "<" is used to specify ZP in the assembler I use
clc
adc #$20
sta <$30
cla
adc #$00
sta <$31


T flag code:

ldx #$30
clc
set
adc #$20
inx
set
adc #$00

The contents of A are not effected when the T flag is set.

Quote:

So the "SET" works like a kind of "prefix" as in other architectures, to modify an opcode. What about the X-indexed addressing modes?
what would

Code:

SET
ADC $02,X


do?

ADC $02,X still functions the same as it would when the T flag is clear.

LDX <$30
CLC
SET
ADC <$00,X

Would at the contents of <$30 to itself and store it back to <$30 (M=M+M). Interrupts save the state of the T flag but clear it right after pushing it to the stack, so there isn't a problem interfering with the interrupt code.

I also forget to mention that the N and Z flags are effect when in decimal mode (V flag isn't). Is this the same case with the new WDC versions? I didn't remember seeing it mentioned in the PDF.


The chip came out in '87 and is not produced anymore as of '96, I believe. I have seen large quantities of old stock available a few months back (mostly HK and JP sites). I know both the HuC6260 and HuC6270, both by Hudson, are easier to find but they aren't CPUs (graphic processors to interface with the huc6280).

The chip was mostly known as the CPU for the PC Engine (one of the first system to use a CD attachment with YellowBook format - back in '88). I currently developing for the PC Engine, but I have two spare systems that I'd like to remove the processor from, for a future project.


Btw if anyone is interested, here is the overview pdf for the mitsubishi e740 6502 variant (thanks to Charles MacDonald) - http://pcedev.net/65xx/e740sum.pdf.

-Rich

[kc5tja]

tomaitheous wrote:

normal code:

lda <$30 ; "<" is used to specify ZP in the assembler I use
clc
adc #$20
sta <$30
cla
adc #$00
sta <$31


T flag code:

ldx #$30
clc
set
adc #$20
inx
set
adc #$00

Hey, that's pretty slick! Thanks for the code example. That cleared everything up for me.

[blargg]

tomaitheous wrote:

Branch instructions that cross a page boundary don't have a penalty cycle.

I may be wrong, but isn't it instead that you don't save a cycle for branches within the same page? That branch takes either 2 clocks (not taken) or 4 clocks (taken)? Perhaps an advantage in simplifying cycle counting, but not in efficiency (assuming I'm not mistaken about this issue).

[GARTHWILSON]

Quote:

That branch takes either 2 clocks (not taken) or 4 clocks (taken)?

With the 65c02:

Branch not taken: 2 clocks
Branch taken, within page: 3 clocks
Branch taken, page boundary crossed: 4 clocks

Most branches (taken) will take 3 clocks.

The 65816 does not need the fourth clock to cross page boundaries in native mode, so it always takes either 2 or 3 clocks.

[kc5tja]

For the record, the reason it takes 4 cycles is because the ALU is only 8-bits wide. The core is intelligent enough to not bother with the high byte of the address if there is no need to. Using a proper 16-bit ALU will eliminate this problem altogether.

[Dr Jefyll]

Huh! It seems I'm late joining the discussion! But I have some additional info on the HuC6280.

I wasn't aware of the HuC6280, but the subject came up when I was jawing with a new acquaintance, Charles MacDonald, on a thread in the pcedev forum. Anyway, it seems the chip has a Wikipedia page now. Also, there's an extensive document that Charles posted on his own site. Section 2.3 deals with the T Flag (which other posters have mentioned above):

Quote:

When the T flag is set, the accumulator is replaced with a zero page memory location indexed by the X register. The operation defined by the instruction is performed using the memory location as one operand, and the effective address as the other. The result is stored in the memory location, leaving the accumulator undisturbed.

This is a capability that really made me sit up and take notice! Sure, the other new features (eg, instructions such as SAX, SAY and BSR) are undeniably cool, but the T Flag is a fundamental improvement, IMHO. Much though we all love the 65xx architecture, the Accumulator has always represented somewhat of a bottleneck in that nearly all arithmetic and logical operands must pass through it -- ie, be loaded beforehand and stored afterward. I'm really intrigued and impressed at how the HuC6280's T Flag manages to transcend that barrier... and yet, the scheme doesn't "break" anything in the pre-existing 65xx architecture. Pretty darn innovative, I'd say!

tomaitheous wrote:

Branch instructions that cross a page boundary don't have a penalty cycle.

I think maybe I've gotten to the bottom of the confusion on this point. A listing of all instructions is found here; this is a link from the Wikipedia article. According to this source, a conditional branch usually "takes one extra cycle if the branch is taken, and another extra cycle if a page boundary is crossed in taking the branch." However, the listings for the BBS and BBR instructions (branch on bit set/reset) do not include this qualification. BBS and BBR are listed as 6-cycle instructions -- evidently allowing enough time (as it fetches from Z-pg) for the CPU to fully resolve the branch destination.

-- Jeff
ps- I notice that Charles McDonald is also cited above, in regard to the mitsubishi e740 6502 variant.

[ElEctric_EyE]

Fascinating. I never head of the Hudson 6280HuC. I wasn't here when tomaitheous started this thread, but it's cool you dug this up Dr. Jeffyl!
One day when I learn verilog, my first project will be to incorporate a compilation of the very best 65x02 designs/ideas. I've thought that the 65CE02 was "the most superior" CPU up until this... Not to ignore the achievements of the '816, but it is still lacking as "the ultimate 65X02" because of a lack of multiple accumulators, more registers, and data exchange between them.

[Dr Jefyll]

ElEctric_EyE wrote:

I wasn't here when tomaitheous started this thread

Neither was I. But it is fascinating. I'm also curious about the mitsubishi e740 6502 variant mentioned earlier in the thread. But the link to that document, e740sum.pdf, is 404, so I just PMed Charles MacDonald to see if it's available at another location.

Quote:

I've thought that the 65CE02 was "the most superior" CPU up until this... Not to ignore the achievements of the '816

Well, all of these chips have their own particular charm. Overall, the 816 is hard to beat. But the CE02 is certainly enviable in terms of pure efficiency -- there are very few if any of the wasted bus cycles common to other implementations. If the CE02 were available in the same 14 MHz process as the '816, I can agree it'd be superior for applications not involving a lot of 16-bit data.

-- Jeff

[BigEd]

Wow - that T mode is very interesting - and we're already familiar with a handful of read-modify-write operations. Now we get 256 accumulators. Or, indeed, 257.

That 740 summary pdf can be found on this page which catalogues Renesas datasheets (they took over some Mitsubishi interests)

[Nightmaretony]

Hudson. the PC-Engine home game system.

[tomaitheous]

The ASL assembler supports the Mitsubishi 65x variant: http://john.ccac.rwth-aachen.de:8000/as/

Apparently from looking over the doc for the assembler, there's also a 16bit version of the original 740. But that's all I know about it.

The SPC700 cpu in the Sony audio unit for the SNES, also appears to be a 65x variant. But it's radically different from anything I've seen. I haven't looked at the opcodes in binary to see how the correspond to the original 65x designs.

Also, on the block transfer instructions. A, X, and Y are pushed onto the stack. So they're used in the instruction. But what baffles me, is that the all three operands are 16bit. And as far as I know there are no 16bit registers on the 6280. Maybe there's an internal shadow set or such, and that's what they uses as a pair. Dunno.