Huh! It seems I'm late joining the discussion! But I have some additional info on the HuC6280.
I wasn't aware of the HuC6280, but the subject came up when I was jawing with a new acquaintance, Charles MacDonald, on
a thread in the pcedev forum. Anyway, it seems the chip has
a Wikipedia page now. Also, there's
an extensive document that Charles posted on
his own site. Section 2.3 deals with the T Flag (which other posters have mentioned above):
Quote:
When the T flag is set, the accumulator is replaced with a zero page memory location indexed by the X register. The operation defined by the instruction is performed using the memory location as one operand, and the effective address as the other. The result is stored in the memory location, leaving the accumulator undisturbed.
This is a capability that really made me sit up and take notice! Sure, the other new features (eg, instructions such as SAX, SAY and BSR) are undeniably cool, but the T Flag is a
fundamental improvement, IMHO. Much though we all love the 65xx architecture, the Accumulator has always represented somewhat of a bottleneck in that nearly all arithmetic and logical operands must pass through it -- ie, be loaded beforehand and stored afterward. I'm really intrigued and impressed at how the HuC6280's T Flag manages to transcend that barrier... and yet, the scheme doesn't "break" anything in the pre-existing 65xx architecture. Pretty darn innovative, I'd say!
tomaitheous wrote:
Branch instructions that cross a page boundary don't have a penalty cycle.
I think maybe I've gotten to the bottom of the confusion on this point. A listing of all instructions is found
here; this is a link from the Wikipedia article. According to this source, a conditional branch usually "takes one extra cycle if the branch is taken, and another extra cycle if a page boundary is crossed in taking the branch." However, the listings for the BBS and BBR instructions (branch on bit set/reset) do not include this qualification. BBS and BBR are listed as 6-cycle instructions -- evidently allowing enough time (as it fetches from Z-pg) for the CPU to fully resolve the branch destination.
-- Jeff
ps- I notice that Charles McDonald is also cited above, in regard to the mitsubishi e740 6502 variant.