Control signals of 6502

[Senijs]

I am trying to make a 6502 work-alike processor in Logisim. I was trying to find info about 6502's control signals/pins/bus, but couldn't find anything except for Hanson's 6502 block diagram where you can see the control signal's names, but nothing about how they actually work.
The reason I want to learn more about 6502's control signals is that my current Logisim 6502 architecture would require over 10 clock cycles to execute a simple instruction, whereas a normal 6502 would do it in 2-3 cycles. How it would do so is a mystery to me and I would like to learn a lot more about the 6502 control signals.

I also tried to reverse-engineer the control signals using visual6502, but I don't know how the debugger there works and couldn't find much information about the debugger either.

Any explanation or documentations of 6502's control signals in depth would be appreciated or any info on visual6502's debugger.

[BigEd]

Hanson's block diagram is a very good place to start - as you've noticed, there's a lot of detail there, in the signal names and their use within the datapath.

The signal names in visual6502 are in many cases inherited from the block diagram, which should help you piece together the way things work.

The use of both clock phases allows the 6502 to make very efficient use of time: three cycles is really four in many cases, because of overlap between consecutive instructions, and four cycles is really eight phases, which might or might not be helpful way to look at things.

You can trace the registers, latches, internal data busses and the datapath control signals, and show behaviour phase by phase, in visual6502. And I think that's worth doing. As with the block diagram, there's lots to study in the tabulation you get.

It might be worth trying to get an independent understanding of a datapath before tackling the very specific 6502. It's possible the nand2tetris book/website/course would be a good way to do that. For myself, I think I learned a lot from Tanenbaum's book, _Structured Computer Organisation_

I'd say visual6502 is a very useful tool, and that there's no need to feel you have to understand the transistor level. It's enough to have a good picture of the datapath, and then to run a simulation like this:
http://visual6502.org/JSSim/expert.html ... ,DPControl

You can then see exactly what's happening in the datapath, and what the datapath control signals are doing.

If you want to run specific instructions, you can do it like this:
http://visual6502.org/JSSim/expert.html ... 056908eaea

[BigEd]

(In terms of cycle count efficiency, I think the 6502 benefits from having three interconnected internal busses - a simpler datapath might need several consecutive cycles to do what the 6502 can do in a single cycle. Also the ALU contains a register which can act as a temporary store, which helps.)

[BigEd]

(It might be worth noting that Hanson's "adder hold register" called 'ADD' is in the visual6502 called 'alu')

[Senijs]

Thanks for the suggestions, BigEd, I'll check out the book and Nand2Tetris project.

I think I should learn more about the 6502 cycles timing. 1 cycle can be thought of, as you said, several cycles really. I remember there being a diagram of 6502 cycles which shows how much action actually happens in just 1 cycle. It looked something like the one in the picture attached to my comment. But I don't know how to read it.

I guess I'll have read up a lot of stuff about the signals, 6502 and also some basics. I'll start with your book.

On another note, I've been thinking that switching from Logisim to, say, Java would be a good idea, since I'd have a lot more control over nuances of my processor. And Logisim suffers from that. Especially racing conditions which you have no control over at Logisim. I guess I'll have to learn Java too haha.

[BigEd]

There's a difficulty with writing a simulation in a conventional programming language: hardware is parallel, and to make a model of a parallel process is not so easy.

If you could share your story of what your model is doing for 10 cycles that might help. It does seem a large number. An add immediate needs to
- read the opcode
- read the operand
- perform the addition
- store to the accumulator and update the flags

[Senijs]

BigEd wrote:

There's a difficulty with writing a simulation in a conventional programming language: hardware is parallel, and to make a model of a parallel process is not so easy.

If you could share your story of what your model is doing for 10 cycles that might help. It does seem a large number. An add immediate needs to
- read the opcode
- read the operand
- perform the addition
- store to the accumulator and update the flags

Yes, that's a great idea. Maybe you can help with my project directly.
It's been a while since I put my hands on this project, so I had to spend some time trying to remember what the problem was. It seems Add with Carry Immediate actually takes only 4 cycles + the fetch phase (3 cycles). The thing really messing with me is Absolute addressing mode and alike. They take 10+ cycles and I can see why- a lot of manipulation with storing and loading data from program counter to memory address register to stack pointer... I'll have to spend some days trying to improve my architecture and somehow cheat my way with racing conditions. I was hoping to find how the real 6502 manages it's control signals to get a lot of my answers answered immediately.

Thank you for spending your time on me and sharing valuable books and resources, BigEd! I'll have to figure out most of this stuff myself, but if I bump into some obstacle again, I'll make sure to ask it via thread.

[BigEd]

One of the neat features inside the 6502 is that the PC is mainly incremented or left alone. So, for example, addressing the three bytes of a long instruction is done by successively incrementing the PC. After the operands have been fetched, the PC naturally points at the next instruction ready for a fetch. (Of course, a few instructions affect the PC directly.)

It helps that operand bytes and zero-page pointers are held low-byte-first, because it means index addition can happen in parallel with fetching the second byte, and the carry from the first addition is available at the right time to affect the high byte.

[Dr Jefyll]

Senijs wrote:

It seems Add with Carry Immediate actually takes only 4 cycles + the fetch phase (3 cycles).

Senijs, it would be more accurate to say Add with Carry Immediate takes 4 half-cycles (since one cycle includes both the Phase 1 period and the Phase 2 period).

You may wish to acquaint yourself with Appendix A of the mcs6500 family hardware manual. This is a cycle-by-cycle description of 6502 operations. It deals in entire cycles only, and does not break each cycle into its Phase 1 and Phase 2 periods. Sometimes it's helpful to consider an overview, with less complexity revealed.

-- Jeff

[Senijs]

Dr Jefyll wrote:

Senijs wrote:

It seems Add with Carry Immediate actually takes only 4 cycles + the fetch phase (3 cycles).

Senijs, it would be more accurate to say Add with Carry Immediate takes 4 half-cycles (since one cycle includes both the Phase 1 period and the Phase 2 period).

-- Jeff

As I understand it, a cycle has a rising phase and a falling phase. If that's so, my Logisim 6502 processor does take 4 full cycles. Which is 8 half cycles. It is very slow.
And as I understand 6502's timing diagram, there is a racing condition going on in it, but the outcome is not random, it's settled. Just like JK flip flop has a racing condition in it. In Logisim you have little control over these racing conditions, but it is managable to cheat through them and use them to your advantage.

I would like to learn more about the clock cycles like demonstrated here viewtopic.php?f=12&t=4370 , but I'm not sure where to find info about it. Rather, I will find a book or a youtube video eventually, but maybe you have a good suggestion on where to read about all this?

[DerTrueForce]

Right at the end of the document Dr Jefyll linked, Appendix A lists cycle-by-cycle breakdowns of what each addressing mode does for each type of instruction. It won't have the CMOS addressing modes, and it's all in text, but it seems mostly clear.

[Dr Jefyll]

Senijs wrote:

As I understand it, a cycle has a rising phase and a falling phase. If that's so, my Logisim 6502 processor does take 4 full cycles.

Alright. I don't know the details of your Logisim 6502 processor, and perhaps the arrangement (or the terminology) is different.

In any case, it will still be helpful to understand the way MOS documents (and many others) refer to clock cycles. Appendix A gives an overview of what appears on the buses during every cycle.