Yet another TTL 6502

[Arlet]

Here's the same area with top layer, showing GND pour, and GND vias near pin 7 of most ICs.

[Arlet]

Here's the same area with bottom layer. Even though most of the traces run here, I still try to allow GND pour between them, especially near the GND pins of the ICs.

Each horizontal row of ICs is one bit slice, and most of the signals are going left to right, which means that most of the return current is also going horizontally. If I put a via near each GND pin, the return current can go through that strip.

I'm still planning to go back to this area and try to move traces in order to maximize the ground flow.

[Arlet]

Hmm.. comparing the schematic with the Verilog code, I realized that I'm missing part of the carry flag logic. I only have carry from adder coming out of ALU, but not the carry I need for shift/rotate.

Easiest solution is to add another 8->1 mux, using the 3 ALU_OP control bits to pick the right carry flag. Feels a bit wasteful to use an 8->1 mux and only use 3 inputs, but with discrete gates I think it will be too messy, and also add more delay. This is also the least amount of work, which is good, because I'm getting tired of board layout. This is only first prototype after all. I can always change things in final version.

[BigEd]

Good spot! I take it you don't have any way to simulate from the schematic?

[Arlet]

In the beginning I had an idea of exporting netlist, and then running a script to convert it to Verilog. It is possible, but probably more work than just carefully hand checking. Most of the datapath is fairly straightforward, with the exception of the BCD logic and flags.

[Dr Jefyll]

Arlet wrote:

Feels a bit wasteful to use an 8->1 mux and only use 3 inputs

3-to-1 analog switches are a thing, and some of them come in 8-pin SMD packages. I haven't checked the switching speeds, supply voltages etc, but perhaps there's one that'll be appropriate for your (impressive and highly entertaining!) project.

-- Jeff

[Arlet]

Quote:

3-to-1 analog switches are a thing, and some of them come in 8-pin SMD packages

An interesting idea. I found one that would work in a nice small package, but it would require a different signal encoding for ALU operation, and rewiring of other ALU mux inputs, so I think I'll stick with the 8->1 switch for now. I will keep it in mind for final version, though.

[Arlet]

Progress has been a bit slow. Lot of other work to do.

I did manage to finish the ALU section, including control lines. Optimized the traces, and added extra GND vias. Also added a bypass cap near each IC (on the bottom, next to the VDD via). Fixed all design rule errors, and put everything on grid in 45 degree angles (using 0.075 mm grid, about 3 mil)

Here's a composite image of all 4 layers (red=top, orange=VDD, yellow=GND, blue=bottom). All layers have GND pour, except the VDD layer which has a pour for the 3.3V power.

[Arlet]

Completed ALU schematic.

[Drass]

Arlet wrote:

Here's a composite image of all 4 layers (red=top, orange=VDD, yellow=GND, blue=bottom). All layers have GND pour, except the VDD layer which has a pour for the 3.3V power.

I think I want that image made into a poster! Honestly, the results are very nice Arlet. Thanks for sharing.

[Arlet]

Didn't have much time today, but I added a couple of control signals for the register clocks. Because these are sensitive to cross talk (unlike everything else) I put them in the GND layer, separated by thin GND strips. There are 4 more clock signals in the design, and the rest is all data/enable which isn't critical.

[shoggoth]

Arlet wrote:

Because these are sensitive to cross talk (unlike everything else) I put them in the GND layer, separated by thin GND strips.

I think you lose a lot doing that, you no longer have a microstrip, and it might make a loop antenna. Could be wrong though.

[Arlet]

How so ? The return current can travel right next to signal, so the 'loop' has minimal enclosed area.

(On the part that you can't see, towards the right, the signals pop back up to top layer, so the GND strips are continuous).

[shoggoth]

It's a solid plane full of current, and there's a slot cut in it, so it may possibly act like a slot antenna. Ground isn't "zero", and voltages are all relative, a slot in a ground plane can be just as bad as a deliberate antenna. I think. It's all theory to me, I don't (intentionally) make transmitters.

I'm pretty sure you don't want any traces passing over those lines on other layers though. In which case why bother doing it on the ground layer, do it on the other layers, since they necessarily have free paths.

It will probably all work anyways though, and you're not going for emissions testing.

[Arlet]

The practical problem is that I only have 2 layers with enough room: the top layer and the 'gnd' layer. Both are relatively clean, and both have a ground pour filling up all unused space, so despite the naming, they are fairly similar.

I don't like to put long traces in top layer, because it tends to cut up the board into little islands. Also, the gnd pins of the devices are directly connected there, so I get "free" connections without having to worry too much about placing a via right next to pin.

What I'm hoping is that the several ground pours together will act as a more or less solid plane (helped by sprinkling of gnd vias)

The only good alternative is to use 6 layers, but I don't think that's necessary for function, and like you said, I'm not going for emissions testing.

I am planning on measuring stuff like cross talk and ground bounce with my scope when I get the boards, and post some results here. One of the advantages of using FPGA as controller is that I don't have to use a 6502 program. I can also do a single "micro op", like making all data lines toggle between 1 and 0 simultaneously.