Serial bootstrap

[GARTHWILSON]

drogon wrote:

Not sure the NMOS ones went over 1Mhz

What I'm finding in my old data books is:

• Synertek: 2MHz
• Rockwell: 3MHz
• Commodore: 3MHz
• GTE (no NMOS)

In the late 1970's Bill Mensch had NMOS 6502's running at 10MHz. That doesn't mean they would pass all the timing margin guarantees at that speed, or that they were guaranteed to run at 10MHz under the whole temperature range. He tells that early production testing was done on a crude, home-made manual tester. If I understood it correctly, the tester was hand-made to approximate the timings of the accompanying parts that a 6502 of so many MHz would have to operate with, which implied that the 6502 met the remainder of the timing margins, and then if it worked at 4MHz, they'd mark it for 2MHz, and it if didn't make it for 4MHz, even by the slimmest of margins, it was marked for 1MHz. IOW, a 1MHz might have actually worked at 3.9MHz, at room temperature.

[drogon]

GARTHWILSON wrote:

drogon wrote:

Not sure the NMOS ones went over 1Mhz

What I'm finding in my old data books is:

• Synertek: 2MHz
• Rockwell: 3MHz
• Commodore: 3MHz
• GTE (no NMOS)

In the late 1970's Bill Mensch had NMOS 6502's running at 10MHz. That doesn't mean they would pass all the timing margin guarantees at that speed, or that they were guaranteed to run at 10MHz under the whole temperature range. He tells that early production testing was done on a crude, home-made manual tester. If I understood it correctly, the tester was hand-made to approximate the timings of the accompanying parts that a 6502 of so many MHz would have to operate with, which implied that the 6502 met the remainder of the timing margins, and then if it worked at 4MHz, they'd mark it for 2MHz, and it if didn't make it for 4MHz, even by the slimmest of margins, it was marked for 1MHz. IOW, a 1MHz might have actually worked at 3.9MHz, at room temperature.

Ah, interesting. Really wasn't aware they went that fast back then. Thanks.

-Gordon

[Michael]

Really? Amazing...

[unclouded]

plasmo wrote:

Can someone describes the first dozen transactions after reset?

This is what I got (from a W65C02S6TPG-14 though). More details here.

Code: Select all

Initialization in progress..
PHI2: L, ADDR: 0000, RWB: L, DATA: 00
PHI2: H, ADDR: ea00, RWB: H, DATA: ea
PHI2: L, ADDR: ea00, RWB: H, DATA: ea
PHI2: H, ADDR: ea00, RWB: H, DATA: ea
PHI2: L, ADDR: ea00, RWB: H, DATA: ea
PHI2: H, ADDR: ea00, RWB: H, DATA: ea
PHI2: L, ADDR: ea00, RWB: H, DATA: ea
PHI2: H, ADDR: ea00, RWB: H, DATA: ea
PHI2: L, ADDR: ea00, RWB: H, DATA: ea
PHI2: H, ADDR: ffff, RWB: H, DATA: ea
PHI2: L, ADDR: ffff, RWB: H, DATA: ea
PHI2: H, ADDR: ea01, RWB: H, DATA: ea
PHI2: L, ADDR: ea01, RWB: H, DATA: ea
PHI2: H, ADDR: 0100, RWB: H, DATA: ea
PHI2: L, ADDR: 0100, RWB: H, DATA: ea
PHI2: H, ADDR: 01ff, RWB: H, DATA: ea
PHI2: L, ADDR: 01ff, RWB: H, DATA: ea
PHI2: H, ADDR: 01fe, RWB: H, DATA: ea
PHI2: L, ADDR: 01fe, RWB: H, DATA: ea
PHI2: H, ADDR: fffc, RWB: H, DATA: 00
PHI2: L, ADDR: fffc, RWB: H, DATA: 00
PHI2: H, ADDR: fffd, RWB: H, DATA: ff
PHI2: L, ADDR: fffd, RWB: H, DATA: ff
PHI2: H, ADDR: ff00, RWB: H, DATA: 4c
PHI2: L, ADDR: ff00, RWB: H, DATA: 4c
PHI2: H, ADDR: ff01, RWB: H, DATA: 00
PHI2: L, ADDR: ff01, RWB: H, DATA: 00
PHI2: H, ADDR: ff02, RWB: H, DATA: ff
PHI2: L, ADDR: ff02, RWB: H, DATA: ff
PHI2: H, ADDR: ff00, RWB: H, DATA: 4c

[Chromatix]

NMOS 6502s were definitely used at 2MHz+ in real products - particularly the BBC Micro (2MHz, 1981) and the earliest versions of its Second Processor (3MHz, 1982). The Apple ][ and C64 were decidedly less ambitious.

The BBC Master upgraded to a 2MHz CMOS version in 1986 - I think the clock speed remained the same because it had to fit with the video output - and around the same time a 4MHz CMOS Second Processor could be fitted internally.

[BigDumbDinosaur]

plasmo wrote:

This is the G8PP+6502 as of a couple hours ago. The series resistors on address lines are not yet added in the photo. Clock is 7.37MHz. Signals look reasonably clean on the scope. I think I'm loading serial data into RAM and observing it bootstrapping after 255 bytes, but it is not executing correctly. There are many moving pieces to this puzzle, one of them is that I don't know much about 6502 assembly instructions. Climbing a steep hill but having fun!
Bill

You, sir, have a counterfeit part.

First off, the logo is not well-formed, which alone would make me declare it to be a fake. Then there is that date code: SA1451, which means the device was fabricated in December 2014. If that were the case, the device would be rated for 14 MHz, not 10, as WDC has not produced a 10 MHz 65C02 in years. Also, the die would have been cut from a wafer produced in TSMC's foundry, which would be noted in the part number.

The part number on a legit PDIP device that would have been made in 2014 would be W65C02S6TPG-14. The 'S' in the part number means it is a static core device (all WDC 65C02s have been static for more than 25 years), '6T' refers to the device's .6µ fabrication geometry and the TSMC foundry, the 'P' means it's a PDIP-40 package, and the 'G' indicates it is RoHS-compliant.

[plasmo]

Thanks for all the inputs. I won't have much time in the next few days to work through them. While the W65C02S8P-10 are clearly not labelled correctly, they appear to work reasonably well at lower clock rate. I tried out several assemblers on my old Windows Vista lab machine. Cross-32 demo does not work, Kowalski assembler kinda work, but Windows Explorer hanged after a while and I had to restart the machine several times. I finally settled on ca65 which actually requires me to read the instruction to use it (If all failed, read the instruction)!

Serial bootstrap is working well and I can load & run 255-byte programs quite well. Wozmon is 256 bytes, so I'll see if I can modify it to run on my SBC. I'm looking for CPU & memory diagnostics.

This is probably it for a while. Merry Christmas to you all!

Bill

[plasmo]

I was able to run the 'fake' W65C02S8P-10 at 3.68MHz and did the ASCII Mandelbrot benchmark in 5 minutes and 55 seconds which is the correct time for a 3.68MHz 6502.

The G8PP platform is designed to accommodate varieties of 8-bit/16-bit processors from 1970's. I have 6 processors in mind: 6502, Z80, 8085, 6809, 68008 and 32008. I've already done the Z80 and 6502 but didn't really want to wire up a single-board G8PP board for every processor, so instead of building all-in-one single-board prototype, I decided I should emulate the RC2014 approach where there are multiple simple CPU boards and a common G8PP baseline board connected via a backplane.

Because each CPU has different control signals and timing requirements, the backplane signal assignments will change depending on the processor used. The addresses and data are the same, so are power/ground, clock, reset, and interrupt. The five Z-80 specific control signals and three spare signals of RC2014 are re-assigned depending on the specific processor. Each processor board is quite simple consists of unbuffered CPU signals connected directly to the 40-pin RC2014 connector.

The common board is the G8PP in baseline configuration. It provides the RESET, clock, battery-backed 512K paged RAM, serial port with bootstrap function, compact flash interface and an Altera EPM7128S CPLD. It also has a prototype area to accommodate additional functions such as RTC, SPI, I2C, etc. The CPLD can be reprogrammed to support different processor's control signals. Such two-board solution has enough functionalities to get CP/M running for the Z80/8085/68008 processors.

Since I've just finished the 6502, I tried out the multi-boards-with-backplane concept on 6502. This is a working configuration with RC2014 Backplane-5.
Bill

[BigEd]

I like this a lot!

[plasmo]

The documentation for my G8PP-based 6502 SBC is here:
https://www.retrobrewcomputers.org/doku ... ppbase6502

I'm off 6502 to work on other 8-bit processors. 65816 looks interesting so I may return later to work on it.
Bill

[BigEd]

Thanks for writing it up!