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ADDRESSING MODES
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MODE SYNTAX OPERAND LOCATION
Implicit: None.
Immediate: #00 Operand is literally the operand byte.
Relative: label Operand byte is 2s-complement offset from byte following it.
Zero Page: $00 Zero-page address follows opcode, operand loaded from there.
Absolute: $0000 16-bit address follows opcode, operand loaded from there.
ZP Index X: $00,X X register is added to zero-page address.
ZP Index Y: $00,Y Y register is added to zero-page address.
Indexed X: $0000,X X register is added to 16-bit address.
Indexed Y: $0000,Y Y register is added to 16-bit address.
ZP Indirect: ($00) Initial address (zero page or absolute) is actually the location
Indirect: ($0000) of the 16-bit address of the operand.
ZP PreIndex: ($00,X) As with Indirect, but the initial address has X added to find
Index Indir: ($0000,X) the location of the 16-bit operand address.
ZP PostIndex: ($00),Y After indirecting, the Y register is added to the address fetched
from zero page. This is useful for iterating over an array.
Some addressing modes are only available with specific instructions, and vice versa.
Most distinct instructions use only the Implicit mode and have no operand; they modify
an internal register and/or perform a stack operation. These include SEC, CLC, SED, CLD,
CLV, SEI, CLI, RTS, RTI, NOP, BRK, STP, WAI, INX, INY, DEX, DEY.
The A-register transfer and ALU instructions form the "main group" and offer the most
flexible addressing modes: LDA, STA, ADC, SBC, AND, ORA, EOR, CMP. Each of these can be
used with Immediate, Zero Page, Absolute, ZP Index X, Indexed X, Indexed Y, ZP Indirect,
ZP PreIndex, and ZP PostIndex - except that STA Immediate does not exist.
Most other instructions are much more restrictive in their choice of addressing mode.
For example, CPX and CPY offer only Zero Page, Absolute, and Immediate modes.
The index registers (X & Y) can only be loaded and stored using Immediate (loads only),
Absolute, Zero Page, Indexed, & ZP Indexed, and can only be indexed by the opposite
index register. LDX and STX are the only users of the ZP Index Y mode. STZ, which
stores a zero, has the same modes as STY.
The shift, rotate & increment instructions exist in two forms: one which operates on the
A-register in Implicit mode (most assemblers will accept A as an operand for clarity),
and one which supports the same addressing modes as STY and performs a read-modify-write
operation. This group is ROR, ROL, ASL, LSR, INC, DEC. The index registers can be
incremented and decremented using the Implicit-mode instructions INX, INY, DEX, DEY.
The logical comparison instruction BIT offers the same addressing modes as LDY. Its
Immediate mode differs subtly from its memory-operand modes in terms of which flags it
sets, so pay attention if you use it.
Branch instructions (all starting with B) can only be used with Relative addressing.
JSR can only be used with Absolute addressing. JMP can be used with Absolute, Indirect,
or Index Indir modes, and is the only instruction that can use the latter two modes.
The SMB and RMB instructions offer only Zero Page mode without indexing. The BBR and BBS
instructions always use a combination of Zero Page and Relative modes. They are also
not available on all CMOS 6502s; in particular they are absent on the 65816. This makes
them less generally useful in practice. Assemblers may omit these instructions if set
to 65sc02 mode.
Generally, if in doubt as to whether a particular instruction supports a particular
addressing mode, either refer to documentation or just see whether your assembler
accepts it.
