128 bit Floating Point 65C816 implementation

[granati]

Hello everyone.

i'm developing a floating point unit for 65C816 compliant with IEEE754 quadruple precision.
At this time these functions are full implemented:
- fpadd, fpsub, fpmult, fpdiv (basic operations)
- fprexp (extract exponent), fscale (scale by a power of two), scale10 (scale by a power of ten), fsquare
- fpack (store in memory in ieee format), funpack (get from memory)
- Roundup functions: ftrunc, fceil, floor, fround, fmod
- str2int, str2fp (convert string to binary)
- fp2str: convert a float to string (compliant with sprintf() function)
- int2dec, uint2dec: convert a 128 bit integer to string
- fsqrt, fcbrt: square root and cube root
- flog, flog10, flog2 (logarithm functions)
- flogp1, flog10p1, flog2p1: computes lognn(1+x) whenn x is very close to 1.0
- fexp, fexp2, fexp10: exponential functions
- fexpm1: computes exp(x)-1 with greater accuracy when x is close to 0.0
- fpown: computes x raised at n (n integer)
- frootn: computes the n-th root
- fpowxy: computes x raised to y (both float)

For future i plan to implement circular functions and hyperbolics functions.

Source code is available HERE: http://65xx.unet.bz/fpu.txt

- Marco

[satpro]

Oh, this is wonderful. I'm going to try it out RIGHT NOW.
...and thank you.

[granati]

Hello everyone,

i updated the fpu implementation with a new version: http://65xx.unet.bz/fpu.txt

Some minor bugs was fixed (one in str2fp function, one in fexp function) and some improvements was done.
Added a function int2str compliant with format of sprintf() function (hex. formatting, a flag to Group thousand in decimal format).

The function that extract integral part and fractionary part was renamed from fmod to fpfrac.

Added two "remainders" functions: fpmod & fprem (work as the same functions in C).

Finally, added circular & hyperbolics functions:

fsin, fcos, ftan, fcotan (max. absolute value of argument: 2^56)
fasin, facos, fatan, fatanyx (this last function compute fatan(y/x) but return value in interval [0, 2pi] useful for computes phase angle)
fsinh, fcosh, ftanh
fasinh, facosh, fatanh

For implementation details and algorithms look at source code.

Greetings,
Marco

[BigDumbDinosaur]

For those who haven't had a peek at Granati's source code, it runs to 9838 lines, which is a substantial piece of work (the entire firmware in my POC is about 11,300 lines). I hope to look more closely into it in the near future, after I recover from my next ( ) eye surgery.

[granati]

BigDumbDinosaur wrote:

For those who haven't had a peek at Granati's source code, it runs to 9838 lines, which is a substantial piece of work (the entire firmware in my POC is about 11,300 lines). I hope to look more closely into it in the near future, after I recover from my next ( ) eye surgery.

Whishes for a quick and good recovery.

Many lines on fpu.asm are just comments, assembled code is about 16k (many bytes used for store float constants).

The main goal is build a "virtual numeric co-processor" with some internal pseudo-registers stack-oriented, interfaced by 'cop' instruction.

[GARTHWILSON]

It's great to have this available online. Thanks Marco. I added it to the math and other software section of my links page.

[BigDumbDinosaur]

granati wrote:

BigDumbDinosaur wrote:

For those who haven't had a peek at Granati's source code, it runs to 9838 lines, which is a substantial piece of work (the entire firmware in my POC is about 11,300 lines). I hope to look more closely into it in the near future, after I recover from my next ( ) eye surgery.

Whishes for a quick and good recovery.

Thank you.

Quote:

Many lines on fpu.asm are just comments, assembled code is about 16k (many bytes used for store float constants).

I include comments in the line count because they have to be typed in, just like the actual instructions, and hence represent code editing time.

The constants tables should help a lot in what are computationally-intensive operations. This is a classic tradeoff between memory consumption and compute-bound performance. Given the much greater addressing capabilities of the 65C816 over the 65C02, memory consumption of this sort should not be a problem.

Quote:

The main goal is build a "virtual numeric co-processor" with some internal pseudo-registers stack-oriented, interfaced by 'cop' instruction.

The BIOS in POC V2 (which is awaiting construction once I regain full use of both eyes) will be called via software interrupts using COP. It'll be an interesting exercise to integrate your floating point package into such an environment.

[johnwbyrd]

Glanced over the code. Thank you for writing it. Looks good.

Is anyone aware whether 32 and 64 bit versions of this code exist?

[tebe6502]

32,64,128 bit

why not, ieee754-16 (half single)

https://en.wikipedia.org/wiki/Half-prec ... int_format

[BigEd]

(Welcome, tebe6502!)

[Chromatix]

The link seems to be dead now. Did anyone save a copy?

[BigEd]

Can see it here:
https://web.archive.org/web/20170923012 ... 80/fpu.txt

[granati]

Sorry for dead link, soon i put again online. Happened when i changed hosting (i restored an old version of the web site).

Marco

p.s.: the source code is available in the downloadable archive in my site

[BigEd]

Great to know you're still active!

[GARTHWILSON]

granati wrote:

p.s.: the source code is available in the downloadable archive in my site

Is that http://65xx.unet.bz/ ? (It's not in your profile or signature line, but it's the base of your link above which gives a 404 error message.) I cannot find the source code in that domain. It is archived though at https://web.archive.org/web/20170923012 ... 80/fpu.txt .