This thread is about the innards of the 8701R2 (revision 2) clock generator chip (used in the C64).

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For instance, it was used in C64 motherboard 250469 rev. B:



The 8701 already went mentioned here in the forum.
A very simplified block diagram of the 8701 is in the lower part of this picture:



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8701 Datasheet, some text with speculations about the pinout.

There are microscopic pictures of the 8701 silicon on Visual6502.org.
From those pictures, to me it looks like the 8701 probably was manufactured in a HMOS-2 process.

Thanks to Michael Steil, Greg James, Christian Sattler, Pavel Zima, Quietust: I'm standing on their shoulders while dissecting the chip.

Polygonized picture of the silicon:



The two pins for the external crystal are South, and that's supposed to be the orientation
for all of the other polygonized pictures in this thread.

Note, that Oscillator plus Bias generator have different GND\VCC pins from the rest of the chip:
Pin 2: GND for Oscillator plus Bias Generator
Pin 9: GND for the rest of the chip
Pin 15: VCC for Oscillator plus Bias Generator
Pin 12: VCC for the rest of the chip

Pavel already did a nice schematic of the 8701R2.

I'm getting almost identical results, from the logic design point of view the little differences don't count:
To me, it looks like the outputs of the counter shift register are not inverters but inverting superbuffers,
and the first two inverters in the Reset input signal line appear to be inverting superbuffers, too.

We have a charge pump, which generates a negative bias voltage for the substrate.

That's for lowering the gate threshold voltage of the FETs on the chip,
resulting in faster speed and lower power consumption.

A nice patent describing the basic concept is here,
except that it's implemented a lot more simple in the 8701,
for instance the detector mentioned in the patent is missing in the 8701.



The big green area in the polygonized picture above is the capacitor at the output of the charge pump,
and the FETs clobbering down positive voltage at the output to GND_Osc are built around that capacitor.

Nothing fancy there:



Edit: output of the driver to the big capacitor is non_inverting, fixed this in the schematic.

I nearly forgot: some more text about the innards of the 8701 is here

Now for the oscillator section.

Recommended reading: Fairchild Application Note AN-340 about CMOS oscillators.


Two interesting areas on the chip:

First picture: (South to Nord)
A dead superbuffer, which seems to be a leftover from a previous revision of the silicon.
Two superbuffers and a FET working as a resistor in parallel.



Second picture: (South to Nord)
Two pads for connecting the external crystal, Input and output.
ESD protection for these pads.
An oddly shaped resistor in the Crystal output signal before it goes to the output pad,
and some part of the big capacitor connected to the Crystal input pad.



Note, that ESD protection for the output pad is connected to GND instead of GND_Osc to simplify the chip layout.

About that oddly shaped resistor in the oscillator output
(PolySilicon "snake" nailed to a metal trace with vias):
I think the designers wanted to be able to increase the resistance without changing the layout by just removing vias, starting from West to East.

Very interesting investigations!

Thanks, Ed. Just one week and a half of work.

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Then we have a superbuffer directly fed by the Crystal input pad:



Which just passes on the inverted oscillator input signal to the Color Clock output buffer.



Note the clock signal /color (inverted color clock), which is tapped from the last stage of the Color Clock output buffer.
It is used for generating the Dot Clock later.

When following the /color signal, we enter an area which (from the logic design point of view)
only contains 4 superbuffers:

Between the area of 4 super buffers and the Color Clock output buffer,
we have an area with delay elements.

Ok, /PAL here is identical to NTSC which is identical to Pin 7 (EnablePAL) of the chip, sorry for the confusion.

Depending on if the chip runs in PAL or NTSC, the delay is selected differently.
There is a reason for this, and don't worry: we are getting there later.





Oh, and we also have two dead inverters which seem to be leftovers from the PAL delay path in a previous revision of the silicon.

Ok, so North of the area of 4 super buffers, we have two logic gates with a "boosted" output:
an XOR gate, and an XNOR gate.

And yes, we are talking about the clock doubler here.

And (East) from there, generating a two phase non overlapping clock signal PHI1 and PHI2
(to be used for clocking the circuitry which later generates the Dot Clock)
out of the XOR\XNOR output signals PH1 and PH2
just circles around creative tinkering with NOR based RS flipflops:

// I'm intentionally breaking the lines of text this way to prevent a "stack overflow" in the brains of the readers.

The concept for the PHI1, PHI2 clock generation from the Color Clock basically breaks down like this:



Of course, when building a clock doubler like this, the best approach is to have signal pulses
of half the /color clock period at the outputs of the XOR\XNOR gates.

Color Clock frequency (and period) is different for PAL and NTSC,
and that's why different time delays for PAL and NTSC are used in the clock doubler.

We continue with the circuitry which generates the Dot Clock after a short break...
because that's going to be a lot of stuff.

I nearly forgot:

Pin 5 is the /RES input, low_active reset signal for the shift register which works as a counter for generating the Dot Clock.

Since there is a pullup resistor inside the chip for Pin 5, Dot Clock generation will work when the pin is not connected (outside the chip).

Ok, now for the hard part:
It's a lot of stuff, and somebody (not me) better should check if I did any mistakes
during reverse_engineering.

The circuitry clocked by PHI1, PHI2 which generates the Dot Clock.

On the silicon, this breaks down into three parts.

First, we have three big NOR gates, plus some and gates and inverters at their inputs:

Second, we have a shift register which works as a counter.








Edit: error fixed, there were two latches too many in 8701_cnt2_3.

Third, we have another shift register plus some logic gates (controlled by the two other blocks mentioned above),
generating a signal which I had named DCLK.
DCLK later goes to the Dot Clock output buffer.

BTW: marking the part of the diffusion layer which happens to be GND with a brighter color sometimes simplifies reverse engineering.

A buried contact in the polygonized images seems to be missing, I had marked the area in question with a little orange rectangle and a question mark.



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Edit: fixed error: an inverter somehow had sneaked into the input of the #OP NOR gate.

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Edit: fixed.

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Edit: fixed.
Edit2: cleaned up.
...And now the simulation is starting to make sense.